Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 108

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
PWM Reload Event
PWM Prescaler
PWM Period and Count Resolution
PWM Output Polarity and Off-State
The default off-state and polarity of the PWM outputs are controlled by the option bits
PWMHI and PWMLO. The PWMHI option controls the off-state and polarity for PWM
high-side outputs PWMH0, PWMH1 and PWMH2. The PWMLO option controls the off-
state and polarity for low-side outputs PWML0, PWML1 and PWML2.
The off-state is the value programmed in the option bit. For example, programming
to 1 makes the off-state of PWMH0, PWMH1 and PWMH2 a High logic value and the
active state a Low logic value. Conversely, programming PWMHI to 0 causes the off-state
to be a Low logic value. PWMLO is programmed in a similar manner.
PWM Enable
The MCEN option bit enables output pairs PWM0, PWM1 and PWM2. If the Motor Con-
trol option is not enabled, the PWM outputs remain in a high-impedance state after reset
and is used as alternate functions like general purpose input. If the Motor Control option is
enabled, following a Power-On Reset (POR) the PWM pins enter a high impedance state.
As the internal reset proceeds, the PWM outputs are forced to the off-state as determined
by the PWMHI and PWMLO off-state option bits.
To prevent erroneous PWM pulse-widths and periods, registers that control the timing of
the output are buffered. Buffering causes all the PWM compare values to update. In other
words, the registers controlling the duty cycle and clock source prescaler only take effect
on a PWM reload event. A PWM reload event is configured to occur at the end of each
PWM period or only every 2, 4, or 8 PWM periods by setting the RELFREQ bits in the
PWM Control 1 Register (PWMCTL1). Software indicates that all new values are ready
by setting the READY bit in the PWM Control 0 Register (PWMCTL0) to 1. When the
READY bit is set to 1, the buffered values take effect at the next reload event.
The prescaler decreases the PWM clock signal by factors of 1, 2, 4, or 8 with respect to the
system clock. The PRES[1:0] bit field in the PWM Control 1 Register (PWMCTL1)
controls prescaler operation. This 2-bit PRES field is buffered so that the prescale value
only changes on a PWM Reload event.
The PWM counter operates in two modes to allow edge-aligned and center-aligned out-
puts. Figures 12 and 13illustrate edge and center-aligned PWM outputs. The mode in
which the PWM operates determine the period of the PWM outputs (PERIOD). The pro-
grammed duty-cycle (PWMDC) and the programmed deadband time (PWMDB) deter-
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Multi-Channel PWM Timer
Product Specification
PWMHI
86