Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 128

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Watchdog Timer Register Definitions
PS028702-1210
Watchdog Timer Reload Unlock Sequence
Watchdog Timer Reload High and Low Byte Registers
WDT Reset in Normal Operation
If configured to generate a Reset when a timeout occurs, the WDT forces the device into
the Reset state. The WDT status bit in the
more information about Reset and the WDT status bit, see the the
Recovery
with its reset value.
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a timeout occurs and
the device is in STOP mode, the WDT initiates a Stop Mode Recovery. Both the WDT
status bit and the STOP bit in the
WDT timeout in STOP mode. For detailed information, see the
Recovery
Writing the unlock sequence to the Watchdog Timer Reload High (WDTH) register
address unlocks the two Watchdog Timer Reload registers (WDTH and WDTL) to allow
changes to the timeout period. These Write operations to the WDTH Register address pro-
duce no effect on the bits in the WDTH Register. The locking mechanism prevents spuri-
ous writes to the reload registers.
The following sequence is required to unlock the Watchdog Timer Reload registers
(WDTH and WDTL) for write access:
1. Write
2. Write
3. Write the appropriate value to the Watchdog Timer reload high register (WDTH).
4. Write the appropriate value to the Watchdog Timer reload low register (WDTL).
All steps of the WDT reload unlock sequence must be written in the order just listed. The
value in the Watchdog Timer Reload registers is loaded into the counter every time a
instruction is executed.
The Watchdog Timer reload high and low byte (WDTH, WDTL) registers (see Tables 69
and 70) form the 16-bit reload value that is loaded into the WDT when a
executes. The 16-bit reload value is {WDTH[7:0], WDTL[7:0]}. Writing to these registers
chapter on page 29. Following a Reset sequence, the WDT Counter is initialized
chapter on page 29.
55H
AAH
to the Watchdog Timer Reload High register (WDTH).
to the Watchdog Timer reload high register (WDTH).
P R E L I M I N A R Y
Reset Status and Control Register
Reset Status and Control Register
Z16FMC Series Motor Control MCUs
Reset and Stop Mode
Product Specification
Reset and Stop Mode
are set to 1 following
WDT
Watchdog Timer
is set to 1. For
instruction
WDT
106