Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 116

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 56. PWM 0–2 H/L Duty Cycle High Byte Register (PWMHxDH, PWMLxDH)
Table 57. PWM 0–2 H/L Duty Cycle Low Byte Register (PWMHxDL, PWMLxDL)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
Field
RESET
R/W
ADDR
Bit Position
[7]
SIGN
[6:0], [7:0]
DUTYH and
DUTYL
PWM 0–2 Duty Cycle High and Low Byte Registers
SIGN
R/W
X
7
7
The PWM 0–2 H/L (High side/Low side) duty cycle high and low byte (PWMxDH and
PWMxDL) registers (see Tables 56 and 57) set the duty cycle of the PWM signal. This 14-
bit signed value is compared to the PWM count value to determine the PWM output.
Reads from these registers always return the values from the temporary holding registers.
The PWM generator does not use the PWM duty cycle value until the next PWM reload
event occurs.
PWM Duty Cycle
Writing a negative value (DUTYH[7] = 1) forces the PWM to be OFF for the full PWM
period. Writing a positive value greater than the 12-bit PWM reload value forces the PWM
to be ON for the full PWM period.
Value (H)
0
1
FF_E390H, FF_E392H, FF_E394H, FF_E396H, FF_E398H, FF_E39AH
FF_E391H, FF_E393H, FF_E395H, FF_E397H, FF_E399H, FF_E39BH
6
6
Duty Cycle Sign
Description
Reserved
Duty cycle is a positive two’s complement number.
Duty cycle is a negative two’s complement number.
Output is forced to the off-state.
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value
(bits 5 and 6 of the High byte are always 0). The value is compared to the
current 12-bit PWM count.
R/W
XX
=
5
5
100
P R E L I M I N A R Y

PWM Duty Cycle Value
---------------------------------------------------------- -
PWM Reload Value
4
4
DUTYL
XXH
R/W
Z16FMC Series Motor Control MCUs
3
3
X_XXXX
DUTYH
R/W
2
2
Multi-Channel PWM Timer
Product Specification
1
1
0
0
94