Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 245

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Z16FMC Series Motor Control MCUs
Product Specification
223
IEOB (Interrupt on End Of Buffer)
The Interrupt on end of buffer bit forces the DMA channel to generate an interrupt when
the buffer is closed. If the DMA is operating in direct mode and the TXLN decrements to
the watermark value (see the
DMA Water Mark
section on page 223) and this bit is set
then a interrupt is also generated.
TXFR (Transfer List)
If the DMA is operating in linked list mode and this bit is set, the DMA uses the next LAR
address in the descriptor for the next descriptor address instead of incrementing the current
DMAxLAR address by 16. This allows looping, true linked lists with buffers following
the descriptor or just transfers to other loops.
EOF (End Of Frame)
If this bit is set, the EOF signal is sent to the peripheral on the final transfer in the buffer
(i.e., TXLN == 1). This action signals the peripheral to close the current frame; it is only
used for on-chip peripherals. This bit is also set if a peripheral requests an End Of Frame
before the buffer transfer is completed.
HALT (Halt after this buffer)
If this bit is set then the DMA stops after this buffer is closed. The DMAxLAR points to
the next descriptor but the descriptor will not be fetched.
CMDSTAT (Command Status)
These four bits are exported to the requesting device on the CMDBUS on the first transfer
of a new buffer. These bits are set by a software write or from the DMA reading the
descriptor. At the end of a buffer these four bits will contain status from the peripheral if
the EOF bit is set. See Zilog’s peripheral devices specifications for definitions of com-
mands and status.
DMA Water Mark
When operating in direct mode the DMAxLAR[23:16] byte is used as a water mark inter-
rupt. If these bits are set to any value other than 0, they are compared to the low byte of the
decremented transfer length during a transfer. If the
bit is set and the upper byte of
IEOB
PS028702-1210
P R E L I M I N A R Y
DMA Controller