Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 151

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 74. LIN-UART Status 0 Register – LIN Mode (UxSTAT0)
PS028702-1210
Bits
0
Bits
Field
RESET
R/W
ADDR
Bits
7
6
5
4
Description (Continued)
CTS – CTS signal
When this bit is read it returns the CTS signal level. If LBEN = 1, the CTS input signal is
replaced by the internal receive data Available signal to provide flow control in loopback mode.
CTS only affects transmission if the CTSE bit = 1.
Description
RDA – Receive Data Available
This bit indicates that the receive data register has received data. Reading the receive data
register clears this bit.
0 = The receive data register is empty.
1 = There is a byte in the receive data register.
PLE – Physical Layer Error
This bit indicates that transmit and receive data do not match when a LIN slave or master is
transmitting; it is caused by a fault in the physical layer or multiple devices driving the bus
simultaneously. Reading the status 0 register or the receive data register clears this bit.
0 = Transmit and receive data match.
1 = Transmit and receive data do not match.
OE – Receive Data and Autobaud Overrun Error
This bit is set just as in normal UART operation if a receive data overrun error occurs. This bit
is also set during LIN slave autobaud if the BRG counter overflows before the end of the auto-
baud sequence, indicating that the receive activity was not an autobaud character or the mas-
ter baud rate is too slow. The ATB status bit will also be set in this case. This bit is cleared by
reading the receive data register.
0 = No autobaud or data overrun error occurred.
1 = An autobaud or data overrun error occurred.
FE – Framing Error
This bit indicates that a framing error (no Stop bit following data reception) is detected. Read-
ing the receive data register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
RDA
R
7
0
PLE
R
6
0
OE
R
5
0
P R E L I M I N A R Y
FF_E201H, FF_E211H
FE
R
4
0
BRKD
Z16FMC Series Motor Control MCUs
R
3
0
TDRE
R
2
1
Product Specification
TXE
R
1
1
LIN-UART
ATB
R
0
0
129