Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 71

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Interrupt Controller
Interrupt Vector Listing
PS028702-1210
The interrupt controller on the Z16FMC products prioritize interrupt requests from on-
chip peripherals and the GPIO port pins. The features of the interrupt controller includes:
•
•
•
The IRQs allow peripheral devices to suspend CPU operation in an orderly manner and
force the CPU to start an ISR. Usually this service routine is involved with exchange of
data, status information, or control information between the CPU and the interrupting
peripheral. When the service routine is completed, the CPU returns to the operation from
which it was interrupted.
System exceptions are non-maskable requests which allow critical system functions to
suspend CPU operation in an orderly manner and force the CPU to start a service routine.
Usually this service routine tries to determine how critical the exception is. When the ser-
vice routine is complete, the CPU returns to the operation from which it was interrupted.
The Z16FMC supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. For more information about interrupt ser-
vicing by the Z16FMC’s ZNeo
(UM0188), which is available for download from the Zilog website.
Table 27 lists all of the available interrupts in order of priority.
Table 27. Interrupt Vectors in Order of Priority
Priority
Highest
Flexible GPIO interrupts:
–
–
Three levels of individually programmable interrupt priority
Software Interrupt Requests (IRQ) assertion
Eight selectable rising and falling edge GPIO interrupts
Four dual-edge interrupts
Program Memory
Vector Address
0004H
0008H
000CH
0010H
0014H
P R E L I M I N A R Y
™
CPU core, refer to the
Programmable
Priority?
No
No
No
Yes
Yes
Z16FMC Series Motor Control MCUs
Interrupt Source
Reset (not an interrupt)
System Exceptions
Reserved
Timer 2
Timer 1
ZNEO CPU User Manual
Product Specification
Interrupt Controller
49