Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 202

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
S
Note:
Slave Address
Figure 35. Data Transfer Format – Master Write Transaction with 10-Bit Address
1st Byte
13. The I
14. If more bytes remain to be sent, return to step 9.
15. When there is no more data to be sent, software responds by setting the STOP bit of
16. If no additional transaction is queued by the Master, software clears the
17. The I
18. The I
If the Slave terminates the transaction early by responding with a Not Acknowledge dur-
ing the transfer, the I
minate the transaction by setting either the STOP bit (end transaction) or the START bit
(end this transaction, start a new one). In this case, it is not necessary for software to set
the FLUSH bit of the I2CCTL Register to flush the data that was previously written but
not transmitted. The I
Not Acknowledge case.
Master Write Transaction with a 10-Bit Address
Figure 35 displays the data transfer format from a Master to a 10-bit addressed Slave.
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (= 0). The transmit operation is carried out in the same manner as 7-
bit addressing.
Follow the procedure below to perform a Master transmit operation to a 10-bit addressed
Slave.
1. Software initializes the MODE field in the I
2. Software asserts the TXI bit of the I
3. The I
sent, the Transmit interrupt asserts.
the I
I
with 7- or 10-bit addressing (I
MODE field selects the address width for this node when addressed as a Slave, not for
the remote Slave. Software asserts the IEN bit in the I
2
C Control Register.
2
2
2
2
2
C Control Register (or START bit to initiate a new transaction).
C Controller shifts the data out of through the SDA signal. When the first bit is
C Controller completes transmission of the data on the SDA signal.
C Controller sends the STOP condition to the I
C interrupt asserts because the I
W=0
A
2
2
C Controller asserts the
C Controller hardware automatically flushes transmit data in this
Slave Address
P R E L I M I N A R Y
2nd Byte
2
C bus protocol allows mixing slave address types). The
2
C Control Register to enable Transmit interrupts.
2
A
C Data Register is empty.
NCKI
Z16FMC Series Motor Control MCUs
2
Data
C Mode Register for Master/Slave mode
11110XX
interrupt and halts. Software must ter-
2
A
2
C bus.
C Control Register.
. The two bits
I2C Master/Slave Controller
Product Specification
Data
XX
A/A
TXI
are the two
bit of the
F/S
180