Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 103

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Bit Position
6
Value (H)
Description (Continued)
Timer Input/Output Polarity – TPOL
This bit is a function of the current operating mode of the timer. It deter-
mines the polarity of the input and/or output signal. When the timer is dis-
abled, the timer output signal is set to the value of this bit.
ONE-SHOT mode – If the timer is enabled, the timer output signal
pulses (changes state) for one system clock cycle after timer Reload.
CONTINUOUS mode – If the timer is enabled, the timer output signal is
complemented after timer Reload.
COUNTER mode – If the timer is enabled, the timer output signal is
complemented after timer reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM SINGLE OUTPUT mode – When enabled, the timer output is
forced to TPOL after PWM count match and forced back to TPOL after
Reload.
CAPTURE mode – If the timer is enabled, the timer output signal is
complemented after timer Reload.
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARE mode – The timer output signal is complemented after timer
Reload.
GATED mode – The timer output signal is complemented after timer
Reload.
0 = Timer counts when the timer input signal is High and interrupts are
generated on the falling edge of the timer input.
1 = Timer counts when the timer input signal is Low and interrupts are
generated on the rising edge of the timer input.
CAPTURE/COMPARE mode – If the timer is enabled, the timer output
signal is complemented after timer Reload.
0 = Counting starts on the first rising edge of the timer Input signal. 
The current count is captured on subsequent rising edges of the timer 
input signal.
1 = Counting starts on the first falling edge of the timer input signal. 
The current count is captured on subsequent falling edges of the timer
input signal.
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Product Specification
Timers
81