Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 154

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 76. LIN-UART Control 0 Register (UxCTL0)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
7
6
5
4
3
LIN-UART Control 0 Register
Description
TEN – Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN – Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTSE – CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The LIN-UART recognizes the CTS signal as an enable control for the transmitter.
PEN – Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled. This bit is overridden by the MPEN bit.
1 = The transmitter sends data with an additional parity bit and the receiver receives an addi-
tional parity bit.
PSEL – Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
TEN
R/W
7
0
Hardware Revision Mode Status Field (MSEL = 111B)
This field indicates the hardware revision of the LIN-UART block.
00_xxx LIN UART hardware rev
01_xxx Reserved
10_xxx Reserved
11_xxx Reserved
The LIN-UART Control 0 register (see Table 76) configures the basic properties of the
LIN-UART’s transmit and receive operations.
REN
R/W
6
0
CTSE
R/W
5
0
P R E L I M I N A R Y
FF_E202H, FF_E212H
PEN
R/W
4
0
PSEL
R/W
Z16FMC Series Motor Control MCUs
3
0
SBRK
R/W
2
0
Product Specification
STOP
R/W
1
0
LIN-UART
LBEN
R/W
0
0
132