Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 177

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
SCK (SSMD = 010,
SPI Protocol Configuration
MOSI, MISO
(SSPO = 0)
CLKPOL = 0)
PHASE = 0,
number of bits per frame is a value other than an integral number of 8 bits by setting
NUMBITS to a value other than 0.
Example
To send 20 bits/frame, set NUMBITS = 5 and read/write 4 bytes per frame. The transmit
data must be left justified and the receive data must be right justified.
The transaction is terminated when the master has no more data to transmit. After the final
bit is transferred, SCLK stops and SS and SSV returns to their default states. If TEOF is
not set on the final byte, a transmit underrun error occurs at this point.
This section describes in detail how to configure the ESPI block for the SPI protocol. In
the SPI protocol the master sources the SCK and asserts slave select signals to one or more
slaves. The slave select signals are typically active Low.
SPI Master Operation
The ESPI block is configured for MASTER mode operation by setting the
the ESPICTL Register. The SSMD field of the ESPI Mode Register is set to 000 for SPI
protocol mode. The
NUMBITS field in the ESPI mode register must be consistent with the Slave SPI devices.
Typically for an SPI master
figured for the ESPI alternate function on the MOSI, MISO and SCK pins. The GPIO for
the ESPI SS pin is configured in alternate function mode as well though software uses any
GPIO pin(s) to drive one or more slave select lines. If the ESPI SS signal is not used to
SS
Figure 29. I2S mode (SSMD = 010)
Phase
SSV=1
Bit7
P R E L I M I N A R Y
,
SSIO = 1
frame n
(may be multiple
bytes)
CLKPOL
and
and
Bit0
Wor
SSPO = 0
SSV=0
bits in the ESPICTL Register and the
Z16FMC Series Motor Control MCUs
Bit7
. The appropriate GPIO pins are con-
frame n + 1
Enhanced Serial Peripheral Interface
Bit0
Product Specification
Bit 7
MMEN
bit =
1
in
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