Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 197

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Transmit Interrupts
Transmit interrupts (
•
•
Writing to the I
Receive Interrupts
Receive interrupts (
received by the I
ister. If the RDRF interrupt is not serviced prior to the completion of the next receive byte,
the I
cleared to prevent receive overruns. A receive interrupt does not occur when a Slave
receives an address byte or for data bytes following a slave address that did not match. An
exception is if the interactive receive mode (
which case receive interrupts occur for all receive address and data bytes in Slave mode.
Slave Address Match Interrupts
Slave address match interrupts (
is in Slave mode and an address is received which matches the unique slave address. The
General Call Address (
GCE
ister to determine if the transaction is a read or write transaction. The General Call
Address and STARTBYTE addresses are also distinguished by the
address (
on the unique slave address or the General Call/STARTBYTE address. The
automatically when the I2CISTAT Register is read.
If configured using the
ing, the most significant 7 bits of the first byte of the transaction are compared against the
SLA[6:0]
the first byte of the transaction is compared against {
second byte is compared against
Arbitration Lost Interrupts
Arbitration Lost interrupts (
in Master mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA). The
The transmit data register is empty and the
The I
–
–
–
2
bit = 1 in the I2CMODE Register. Software verifies the
C Controller holds SCL Low during the final data bit of the next byte until
The first bit of a 10-bit address is shifted out
The first bit of the final byte of an address is shifted out and the
serted
The first bit of a data byte is shifted out
GCA
2
C Controller is enabled, with any one of the following:
bits of the Slave Address Register. If configured for 10-bit slave addressing,
) bit of the I2CISTAT Register indicates whether the address match occurred
2
C Data Register always clears the
2
C Controller. The
RDRF
TDRE
0000_0000
MODE[1:0]
bit =
bit = 1 in I2CISTAT) occur under the following conditions:
P R E L I M I N A R Y
ARBLST
1
SAM
SLA[7:0]
in I2CISTAT) occur when a byte of data has been
) and STARTBYTE (
RDRF
field of the I
bit = 1 in I2CISTAT) occur when the I
bit =
bit is cleared by reading from the I
1
.
in I2CISTAT) occur when the I
IRM
Z16FMC Series Motor Control MCUs
TXI
) bit is set in the I2CMODE Register in
2
C Mode Register for 7-bit slave address-
TRDE
bit = 1 in the I
11110
0000_0001
bit to 0.
,
SLA[9:8]
RD
I2C Master/Slave Controller
Product Specification
bit in the I2CISTAT Reg-
2
RD
C Control Register
) are recognized if the
bit. The general call
, R/W} and the
2
C Controller is
2
RD
SAM
C Controller
2
C Data Reg-
bit is deas-
bit clears
RDRF
is
175