Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 146

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Noise Filter
PS028702-1210
Architecture
2. Load the appropriate 16-bit count value into the LIN-UART baud rate high and low
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
When configured as a general purpose timer, the BRG interrupt interval is calculated using
the following equation:
UART BRG Interrupt Interval (s)
A noise filter circuit is included to filter noise on a digital input signal, such as UART
receive data, before the data is sampled by the block. This noise filter circuit is a require-
ment for protocols operating in a noisy environment.
The noise filter includes following features:
•
•
•
•
•
Figure 20 displays how the noise filter is integrated with the LIN-UART for use on a LIN
network.
byte registers.
the LIN-UART Control1 register to 1. Enable the UART receive interrupt in the
interrupt controller.
Synchronizes the receive input data to the system clock
Noise filter enable (
0) or included (
Noise filter control (
counter digital filter. The available widths range is from 4 to11 bits
The digital filter output has hysteresis
Provides an active low saturated state output (
noise
NFEN
NFEN)
NFCTL[2:0])
= 1) in the receive data path
P R E L I M I N A R Y
input selects whether the noise filter is bypassed (
input selects the width of the up/down saturating
=
System Clock Period (s)
Z16FMC Series Motor Control MCUs
FiltSatB
), used to indicate presence of
Product Specification

BRG[15:0]
LIN-UART
NFEN
=
124