Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 275

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 148. IPO Trim 1 (IPOTRIM1)
Table 149. IPO Trim 2 (IPOTRIM2)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Note: L = Loaded at Reset. R/W = Read/Write. This register is loaded from Information area on Reset.
Bits
Field
RESET
R/W
ADDR
Note: L = Loaded at Reset. R/W = Read/Write. This register is loaded from Information area on Reset.
Information Area
IPO Trim registers (Information Area Address 0021H and 0022H)
ADC Reference Voltage Trim (Information Area Address 0023H)
Note:
R/W
R/W
7
L
7
L
Data in the information area of memory cannot be altered directly. If you wish to alter the
factory settings, it must be performed by writing to the Register Address identified. The
part defaults to the factory settings after reset and the registers must be rewritten to have
the user settings in effect. Read the information area address to determine the factory set-
tings.
Tables 148 and 149 define the IPO Trim settings. They are altered after reset by accessing
the IPOTRIM1 and IPOTRIM2 registers.
The IPO Trim table values have yet to be determined.
Table 150 defines the ADC Reference Voltage Trim settings. They are altered after reset
by accessing the ADCTRIM register.
R/W
R/W
6
L
6
L
IPO TEMP TRIM
R/W
R/W
5
L
5
L
P R E L I M I N A R Y
R/W
R/W
FFFF_FF25H
4
L
4
L
FFFF_FF26
IPO TRIM
R/W
R/W
Z16FMC Series Motor Control MCUs
3
L
3
L
R/W
R/W
2
L
2
L
Product Specification
R/W
R/W
1
L
1
L
IPO TRIM
Option Bits
R/W
R/W
0
L
0
L
253