Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 170

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

ESPI Register Overview
PS028702-1210
Slave Select
Comparison with Basic SPI Block
The SS signal is a bidirectional framing signal with several modes of operation to support
SPI and other synchronous serial interface protocols. The SLAVE SELECT mode is
selected by the SSMD field of the ESPI mode register. The direction of the SS signal is
controlled by the SSIO bit of the ESPI mode register. The SS signal is an input on slave
devices and is an output on the active master device. Slave devices ignore transactions on
the bus unless their slave select input is asserted. In SPI MASTER mode, additional GPIO
pins are required to provide Slave Selects if there is more than one slave device.
The ESPI Control/Status Registers are summarized in Table 84. These registers are
accessed by either Word (16-bit) or Byte operations.
Table 84. ESPI Registers
The ESPI module includes many enhancements when compared to the simpler SPI mod-
ule in other Z8 Encore!
module and the SPI module as follows:
•
•
•
•
•
•
Word Address
XXXXX0
XXXXX2
XXXXX4
XXXXX6
Transmit and receive data buffer register added to support higher performance.
Multiple interrupt sources (transmit data, receive data, errors). SPI module only has
data transfer complete interrupt.
DMA controller interface (separate transmit and receive interfaces).
Register addresses redefined to facilitate 16-bit transfers on the Z16FMC.
Transmit data command register: a new register to facilitate the DMA interface and im-
prove performance with 16-bit transfers. SSV and TEOF are set on the same cycle upon
which the data register is written.
Control register:
–
IRQE changed to DIRQE to allow data interrupts to be disabled when using the
DMA but still allow error interrupts
Even Address
Data
Control
Status
Baud Rate High
®
parts. This section highlights the differences between the ESPI
P R E L I M I N A R Y
Odd Address
Transmit Data Command
Mode
State
Baud Rate Low
Z16FMC Series Motor Control MCUs
Enhanced Serial Peripheral Interface
Product Specification
148