Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 175

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Z16FMC Series Motor Control MCUs
Product Specification
153
or DMA request is being serviced (set TEOF before or simultaneously with writing the
final data byte). When the final bit of the final character is transmitted, the hardware will
automatically deassert the SSV and TEOF bits. The second method is for software to
directly clear the SSV bit after the transaction completes. If software clears the SSV bit
directly, it is not necessary for software to also set the TEOF bit on the final transmit byte.
After writing the final transmit byte, the end of the transaction is detected by waiting for
the final RDRF interrupt or monitoring the TFST bit in the ESPI Status Register.
The transmit underrun and receive overrun errors do not occur in an SPI mode master. If
the RDRF and TDRE requests have not been serviced before the current byte transfer
completes, SCLK is paused until the data register is read and written. The transmit under-
run and receive overrun errors will occur in a slave if the slave’s software/DMA does not
keep up with the master data rate. If a transmit underrun occurs in SLAVE mode, the shift
register in the slave is loaded with all 1s.
In the SPI mode, the SCK is active only for the data transfer with one SCK period per bit
transferred. If the SPI bus has multiple slaves, the slave select lines to all or one of the
slaves must be controlled independently by software using GPIO pins.
Figure 28 displays multiple character transfer in SPI mode. Note that while character ’n’ is
being transferred using the shift register, software/DMA responds to the receive request
for character n-1 and the transmit request for character n+1.
PS028702-1210
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface