Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet
Z16FMC32AG20SG
Specifications of Z16FMC32AG20SG
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Z16FMC32AG20SG Summary of contents
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... Motor Control MCUs Z16FMC Series Product Specification PS028702-1210 ® Copyright ©2010 Zilog Inc. All rights reserved. www.zilog.com ...
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... OR OTHERWISE. The information contained within this document has been verified according to the general principles of elec- trical and mechanical engineering. Z8, Z8 Encore!, ZNEO and Z16FMC are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. ...
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... Revision Level Section December 02 Packaging 2010 November 01 2010 PS028702-1210 Z16FMC Series Motor Control MCUs Description Minor corrections to the Zilog Part Numbers table and to the Part Number Suffix Designa- tions map. Original issue Product Specification iii Page No. 311, 312 N/A Revision History ...
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Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Port C IRQ MUX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Synchronized Current-Sense Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . 90 PWM Timer and Fault Interrupts . . . . ...
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LIN-UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ESPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ADC0 Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Memory Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 UART Mode ...
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SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1. Z16FMC Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 31. ESPI Configured as an SPI Master in a Single Master and Multiple Slave System . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 65. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 33. Interrupt Request 1 Register (IRQ1) and Interrupt Request 1 Set Register (IRQ1SET ...
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Table 66. PWM Output Control Register (PWMOUT 102 Current-Sense Sample and Hold Control Register (CSSHR0 Table ...
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Table 101. I2C Control Register (I2CCTL 197 ...
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Table 137. Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Table ...
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... Table 181. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Table 182. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Table 183. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Table 184. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Table 185. Z16FMC Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Table 186. Zilog Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 PS028702-1210 Z16FMC Series Motor Control MCUs Product Specification ...
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... Introduction Zilog’s Z16FMC Series of products is optimized for motor control applications. The Z16FMC is a 16-bit microcontroller with a ZNeo of Zilog’s Motor Control Family of MCUs. Features The Z16FMC Series of products includes the following features: 20 MHz ZNeo • 128 KB internal Flash memory with 16-bit access and In-Circuit Programming (ICP) • ...
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... I C (3) (2) IrDA Figure 1. Z16FMC Series Block Diagram ZNEO CPU Features Zilog’s Z16FMC is powered by the ZNeo faster and more code-efficient microcontrollers. The ZNeo 8-bit, 16-bit and 32-bit ALU operations • 24-bit stack with overflow protection • PS028702-1210 Z16FMC Series Motor Control MCUs 40° ...
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... Like Flash memory, the ZNEO CPU simultaneously accesses 16 bits of internal RAM to improve processor performance. Motor Control Peripherals Overview Zilog’s motor control peripherals are briefly described in this section. 10-Bit Analog-to-Digital Converter with Programmable Gain Amplifier The ADC converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from 12 different analog input sources ...
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General-Purpose Input/Output The Motor Control MCUs features 46 GPIO pins. Each pin is individually programmable. Universal Asynchronous Receiver/Transmitter The Z16FMC MCU contains two fully-featured UARTs with LIN protocol support. UART communication is full-duplex and capable of handling asynchronous data transfers. ...
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PWM pins during Fault condition. Standard Timers Three 16-bit reloadable timers are used for timing/counting events and PWM signal gener- ation. These timers provide a 16-bit ...
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Signal and Pin Descriptions The Motor Control MCUs products are available pin LQFP package. This chapter describes the signals and pin configuration for the LQFP package style. For more informa- tion about the physical package specification, see ...
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PA0/T0IN/T0OUT 49 PD2/PWMH2 PC2/SS RESET VDD PE4 PE3 VSS 56 PE2 PE1 PE0 VSS PD1/PWML1 PD0/PWMH1 XOUT XIN 64 1 Figure 2. Z16FMC in the 64-Pin Low-Profile Quad Flat Package (LQFP) PS028702-1210 Z16FMC Series Motor Control MCUs 40 33 ...
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Signal Descriptions Table 1 describes the Motor Control MCUs signals. To determine the signals available for the LQFP package, see the described in Table 1 are multiplexed with GPIO pins. These signals are available as alter- nate functions on the ...
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Table 1. Signal Descriptions (Continued) Signal Mnemonic I/O RXD0 I CTS0 I DE0 O General-Purpose Timers T0OUT/T0OUT O T1OUT/T1OUT T2OUT/T2OUT T0IN/T0IN1/T0IN2 I /T1IN/T2IN Pulse-Width Modulator for Motor Control PWMH0/PWMH1/ O PWMH2 PWML0/PWML1/ O PWML2 FAULT0/FAULTY I Analog ANA[11:0] ...
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Table 1. Signal Descriptions (Continued) Signal Mnemonic I/O XIN I XOUT O On-Chip Debugger DBG I/O Caution: Reset RESET I/O Power Supply VDD I AVDD I VSS I AVSS I Pin Characteristics Table 2 lists information about the characteristics of ...
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Table 2. Pin Characteristics of the Z16FMC Symbol Reset Mnemonic Direction Direction AVDD N/A N/A AVSS N/A N/A DBG I/O I PA[7:0] I/O I PB[7:0] I/O I PC[7:0] I/O I PD[7:0] I/O I PE[7:0] I/O I PF[7:0] I/O I PG[7:0] ...
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Address Space The Z16FMC CPU offers a unique architecture with a single, unified 24-bit address space. It supports up to three memory areas: Internal non-volatile memory (Flash, EEPROM, EPROM, or ROM). • Internal RAM. • Internal I/O memory (internal peripherals). ...
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Internal I/O Memory Reserved Internal RAM Reserved Internal Non-Volatile Memory To determine the amount of internal RAM and internal non-volatile memory available for the specific device, see the Internal Non-Volatile Memory Internal non-volatile memory contains executable program code, constants and ...
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... Some control registers are reserved I/O memory for the Z16FMC control. These registers are listed in Table 4. For detailed information about the operation of the Z16FMC control registers, refer to the ZNEO CPU User Manual (UM0188), available for download at www.zilog.com. PS028702-1210 Z16FMC Series Motor Control MCUs ...
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Table 4. ZNeo CPU Control Registers Address (Hex) FF_E004-FF_E007 FF_E00C-FF_E00F FF_E010 FF_E012 Endianness The Z16FMC CPU accesses data in big endian order, i.e., the address of a multi-byte word or quad points to the most significant byte. Figure 4 displays ...
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Word operation takes one memory access and a Quad operation takes two memory accesses. If the address odd boundary (unaligned), a Word operation takes two memory accesses and a Quad operation takes three memory accesses. ...
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Peripheral Address Map Table 5 provides the address map for the peripheral space of the Z16FMC Series of prod- ucts. Not all devices and package styles in the Z16FMC Series support all peripherals or all GPIO ports. Registers for unimplemented ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description IRQ2 Enable Low Bit FF_E03B Reserved FF_E03C-FF_E03F Watchdog Timer Base Address = FF_E040 Reserved FF_E040-FF_E041 Watchdog Timer Reload FF_E042 High Byte Watchdog Timer Reload FF_E043 Low Byte Reserved FF_E044-FF_E04F ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description Oscillator Control FF_E0A0 Oscillator Divide FF_E0A1 GPIO Base Address = FF_E100 GPIO Port A Base Address = FF_E100 Port A Input Data FF_E100 Port A Output Data FF_E101 Port ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description Port C Output Data FF_E121 Port C Data Direction FF_E122 Port C High Drive Enable FF_E123 Port C Alternate Function High FF_E124 Port C Alternate Function Low FF_E125 Port ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description Port E Stop Mode Recovery FF_E148 Enable Port E Reserved FF_E149-FF_E14F GPIO Port F Base Address = FF_E150 Port F Input Data FF_E150 Port F Output Data FF_E151 Port ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description Port H Alternate Function Low FF_E175 Port H Output Control FF_E176 Port H Pull-Up Enable FF_E177 Port H Stop Mode Recovery FF_E178 Enable Port H Reserved FF_E179-FF_E17F Serial Channels ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description Base Address = FF_E240 Data FF_E240 Interrupt Status FF_E241 Control FF_E242 Baud Rate High ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description Timer 1 Reload High Byte FF_E312 Timer 1 Reload Low Byte FF_E313 Timer 1 PWM High Byte FF_E314 Timer 1 PWM Low Byte FF_E315 Timer 1 Control 0 FF_E316 ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description PWM Reload High Byte FF_E38E PWM Reload Low Byte FF_E38F PWM 0 High Side Duty Cycle FF_E390 High Byte PWM 0 High Side Duty Cycle FF_E391 Low Byte PWM ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description DMA0 Control0 FF_E410 DMA0 Control1 FF_E411 DMA0 Transfer Length High FF_E412 DMA0 Transfer Length Low FF_E413 Reserved FF_E414 DMA0 Destination Address Upper DMA0DARU FF_E415 DMA0 Destination Address High FF_E416 ...
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Table 5. Register File Address Map (Continued) Address (Hex) Register Description DMA Channel 2 Base Address = FF_E430 DMA2 Control0 FF_E430 DMA2 Control1 FF_E431 DMA2 Transfer Length High FF_E432 DMA2 Transfer Length Low FF_E433 Reserved FF_E434 DMA2 Destination Address Upper ...
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... Comparator and Op-Amp Control CMPOPC FF_E510 Reserved FF_E511 ADC Sample Timer Capture High ADCTCAPH FF_E512 ADC Sample Timer Capture Low FF_E513 Option Trim Registers Base Address = FF_FF00 Reserved for internal Zilog FF_FF00-FF_FF24 IPO Trim 1 FF_FF25 IPO Trim 2 FF_FF26 ADC Reference Voltage Trim FF_FF27 Note: XX=Undefined. ...
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Reset and Stop Mode Recovery The reset controller within the Z16FMC Series controls the RESET and Stop Mode Recovery operations typical operation, the following events cause a Reset to occur: Power-On Reset • Voltage Brownout • WDT timeout ...
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System Reset During a System Reset, the Z16FMC device is held in Reset for 66 cycles of the IPO. At the beginning of Reset, all GPIO pins are configured as inputs. All GPIO programmable pull-ups are disabled. At the start ...
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Power-On Reset Each device in the Z16FMC Series contains an internal POR circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level. After the supply ...
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Reset state. While the supply voltage remains below the POR voltage threshold (V When the supply voltage exceeds the V through a full System Reset sequence, as described in the 31. Following Power-On Reset, the ...
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External Pin Reset The input-only RESET pin has a schmitt-triggered input, an internal pull-up, an analog fil- ter and a digital filter to reject noise. After the RESET pin is asserted for at least four sys- tem clock cycles, the ...
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Mode Recovery, the device is held in Reset for 66 cycles of the internal precision oscilla- tor. Stop Mode Recovery only affects the contents of (see page 35) and the does not affect any other values in the register file, ...
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Reset Status and Control Register The Reset Status and Control Register (RSTSCR, Table 9) records the cause of the most recent RESET or Stop Mode Recovery. All status bits are updated on each RESET or Stop Mode Recovery event. Table ...
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Low-Power Modes Z16FMC products contain advanced integrated power-saving features. Power manage- ment functions are divided into three categories to include CPU operating modes, periph- eral power control and programmable option bits. The highest level of power reduction is provided through ...
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The PC stops incrementing • The WDT’s internal RC oscillator continues to operate • If enabled, the WDT continues to operate • All other on-chip peripherals continue to operate • Any of the following operations can cause the CPU to ...
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General-Purpose Input/Output The Z16FMC products contain general-purpose input/output (GPIO) pins arranged as Ports A–H. Each port contains control and data registers. The GPIO control registers are used to determine data direction, open-drain, output drive current and alternate pin func- tions. ...
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Port Output Control Port Output Data Register Data D Q Bus System Clock Port Data Direction Figure 8. GPIO Port Pin Block Diagram GPIO Alternate Functions Many GPIO port pins are used for GPIO and to provide access to the ...
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Table 12. Port Alternate Function Mapping Port Pin Alternate Function 1 Port A PA0 T0IN/T0OUT PA1 T0OUT PA2 DE0 PA3 CTS0 PA4 RXD0 PA5 TXD0 PA6 SCL PA7 SDA Port B PB0/T0IN0 ANA0 PB1/T0IN1 ANA1 PB2/T0IN2 ANA2 PB3 ANA3/OPOUT PB4 ...
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Table 12. Port Alternate Function Mapping (Continued) Port Pin Alternate Function 1 Port E PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Port F PF7 Port G PG3 Port H PH0 ANA8 PH1 ANA9 PH2 ANA10 PH3 ANA11/CPINP GPIO Interrupts ...
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Table 13. Port A–H Input Data Registers (PxIN) Bits 7 6 Field PIN7 PIN6 RESET ADDR FF_E100, FF_E110, FF_E120, FF_E130, FF_E140, PIN[7:0] – Port Input Data Sampled data from the corresponding port pin input. 0 ...
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Table 15. Port A–H Data Direction Registers (PxDD) Bits 7 6 Field DD7 DD6 RESET 1 1 R/W R/W R/W ADDR FF_E102, FF_E112, FF_E122, FF_E132, FF_E142, DD[7:0] – Data Direction These bits control the direction of the associated port pin. ...
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Writes to the port alternate function high and low registers. Do not enable alternate functions for GPIO port pins which ...
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Table 20. Port A–H Output Control Registers (PxOC) Bits 7 6 Field POC7 POC6 RESET 0 0 R/W R/W R/W ADDR FF_E106, FF_E116, FF_E126, FF_E136, FF_E146, POC[7:0] – Port Output Control These bits function independently of the alternate function bits ...
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STOP mode, any logic transition on a port pin enabled as a Stop Mode Recovery source initiates Stop Mode Recovery. Table 22. Port A–H Stop Mode Recovery Source Enable Registers (PxSMRE) Bits 7 6 Field PSMRE7 PSMRE6 RESET 0 0 ...
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Port A IRQ MUX Register The Port IRQ MUX register (see Table 24) selects either Port A or Port D pins as interrupt sources. Table 24. Port A IRQ MUX Register (PAIMUX) Bits 7 6 Field PAIMUX7 PAIMUX6 PAIMUX5 PAIMUX4 ...
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Port C IRQ MUX Register The Port C IRQ MUX register (see Table 26) selects either Port C pins or the DMA chan- nels as interrupt sources. Table 26. Port C IRQ MUX Register (PCIMUX) Bits 7 6 Field Reserved ...
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... The Z16FMC supports both vectored and polled interrupt handling. For polled interrupts, the interrupt control has no effect on operation. For more information about interrupt ser- vicing by the Z16FMC’s ZNeo (UM0188), which is available for download from the Zilog website. Interrupt Vector Listing Table 27 lists all of the available interrupts in order of priority. ...
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Table 27. Interrupt Vectors in Order of Priority (Continued) Program Memory Priority Vector Address 0018H 001CH 0020H 0024H 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H Lowest 006CH PS028702-1210 Z16FMC Series ...
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The most significant byte (MSB) of the four-byte interrupt vector is not used. The vector is stored in the three least significant bytes (LSB) of the vector, as shown in Table 28. Table 28. Interrupt Vector placement Vector Byte 0 ...
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Master Interrupt Enable The master interrupt enable bit in the flag register globally enables or disables interrupts. This bit has been moved to the flag register (bit 0). Thus, anytime the register is loaded, it changes the state of the ...
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When this happens the processor again vectors to the system exception vector and sets the associated exception status bit. The ser- vice routine would then have to respond to the new exception. Upon illegal ...
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Bits Description (Continued) 4 DIVOVF – Divide Over Flow If this bit divide overflow occurred. A divide overflow happens when the result is greater than FFFFFFFFH. Writing this bit clears ...
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Table 31. Last IRQ Register (LASTIRQ) Bits 7 6 Field Always 0 RESET 0 0 R/W R R/W ADDR Interrupt Request 0 Register The Interrupt Request 0 (IRQ0) Register, shown in Table 32, stores the interrupt requests for both vectored ...
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Bits Description (Continued) 5 T0I – Timer 0 Interrupt Request interrupt request is pending for timer interrupt request from timer 0 is awaiting service. Writing this bit Resets it to ...
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Table 33. Interrupt Request 1 Register (IRQ1) and Interrupt Request 1 Set Register (IRQ1SET) Bits 7 6 Field PAD7I PAD6I RESET 0 0 R/W R/W1C R/W1C ADDR Field PAD7I PAD6I RESET ADDR Note: IRQ1SET at ...
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Table 34. Interrupt Request 2 Register (IRQ2) and Interrupt Request 2 Set Register (IRQ2SET) Bits 7 6 Field PWMTI U1RXI RESET 0 0 R/W R/W1C R/W1C ADDR Field PWMTI U1RXI RESET ADDR Note: IRQ2SET at ...
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IRQ0 Enable High and Low Bit Registers The IRQ0 enable high and low bit registers (shown in Tables 36 and 37) form a priority encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated by setting bits ...
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Table 37. IRQ0 Enable Low Bit Register (IRQ0ENL) Bits 7 6 Field T2ENL T1ENL RESET 0 0 R/W R/W R/W ADDR Bits Description 7 T2ENL Timer 2 Interrupt Request Enable Low Bit 6 T1ENL Timer 1 Interrupt Request Enable Low ...
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Table 39. IRQ1 Enable High Bit Register (IRQ1ENH) Bits 7 6 Field PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH RESET 0 0 R/W R/W R/W ADDR Note: PADxENH = Port A/D Bit[x] Interrupt Request Enable High Bit Table 40. ...
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Table 42. IRQ2 Enable High Bit Register (IRQ2ENH) Bits 7 6 Field PWMTENH U1RENH RESET 0 0 R/W R/W R/W ADDR Bits Description 7 PWMTENH PWM Timer Interrupt Request Enable High Bit. 6 U1RENH UART 1 Receive Interrupt Request Enable ...
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Bits Description (Continued) 4 PWMFENL PWM Fault Interrupt Request Enable Low Bit 3:0 CxENL/DMAxENL Port Cx or DMAx Interrupt Request Enable Low Bit. PS028702-1210 Z16FMC Series Motor Control MCUs ...
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Timers The Z16FMC contains three 16-bit reloadable timers used for timing, event counting, or generation of pulse width modulated (PWM) signals. Features The timers include the following features: 16-bit reload counter • Programmable prescaler with values ranging from 1 to ...
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Data Bus Block Control System Clock Timer Input Gate Input Capture Input Operation The general-purpose timer is a 16-bit up-counter. In normal operation, the timer is initial- ized to . When the timer is enabled, it counts up to the ...
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Timer Operating Modes The timers are configured to operate in the following modes: ONE-SHOT Mode In ONE-SHOT mode, the timer counts up to the 16-bit reload value stored in the Timer Reload High and Low byte registers. The timer input ...
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TRIGGERED ONE-SHOT Mode In TRIGGERED ONE-SHOT mode, the timer operates as follows: 1. The timer is non-active until a trigger is received. The timer trigger is taken from the timer input pin. The TPOL bit in the Timer Control 1 ...
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CONTINUOUS Mode In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the timer reload high and low byte registers. After reaching the Reload value, the timer gener- ates an interrupt, the count value in the ...
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The input frequency of the timer input signal must not exceed one-fourth the sys- Caution: tem clock frequency. In COMPARATOR COUNTER mode, the timer counts output transitions from an analog comparator output. The timer takes its input from the ...
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PWM SINGLE and DUAL OUTPUT Modes In PWM SINGLE OUTPUT mode, the timer outputs a PWM output signal through a GPIO Port pin. In PWM DUAL OUTPUT mode, the timer outputs a PWM output signal and also its complement through ...
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The PWM period is determined by the following equation: PWM Period( initial starting value other than isters, use the ONE-SHOT mode equation to determine the first PWM timeout period. If TPOL is set to 0, the ratio ...
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On reaching the Reload value, the timer gener- ates an interrupt and continues counting. CAPTURE RESTART Mode When the timer is enabled in CAPTURE RESTART mode, it counts continuously until the capture event ...
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Write to the Timer Control 1 Register to enable the timer. In CAPTURE and CAPTURE RESTART modes, the timer begins counting. In CAPTURE COMPARE mode the timer does not start counting until the first appropriate input transition occurs. In ...
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Compare Mode Time(s) = GATED Mode In GATED mode, the timer counts only when the timer input signal is in its active state as determined by the TPOL bit in the Timer Control 1 Register. When the timer input signal ...
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Reading Timer Count Values The current count value in the timer is read while counting (enabled). This has no effect on timer operation. Normally, the count must be read with one 16-bit operation. However, 8-bit reads are performed using with ...
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Bits Description 7:0 TH – Timer High Byte TH is one of two bytes {TH[7:0], TL[7:0]} which contain the current 16-bit timer count value. Table 45. Timer 0–2 Low Byte Register (TXL) Bits 7 6 Field RESET R/W ADDR Bits ...
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Table 47. Timer 0–2 Reload Low Byte Register (TxRL) Bits 7 6 Field RESET R/W ADDR Bits Description 7:0 TRL – Timer Reload Register Low TRL is one of two bytes which form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This ...
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Table 49. Timer 0–2 PWM Low Byte Register (TxPWML) Bits 7 6 Field RESET R/W ADDR Bits Description 7:0 PWML – Pulse-Width Modulator Low Byte PWHL is one of two bytes, {PWMH[7:0], PWML[7:0]}, which form a 16-bit value that is ...
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Bit Position Value (H) Description (Continued) 6:5 Timer Interrupt Configuration – TICONFIG This field configures timer interrupt definitions. These bits affect all modes. The effect per mode is explained below: ONE SHOT, CONTINUOUS, COUNTER, PWM, COMPARE, DUAL PWM, TRIGGERED ONE-SHOT, ...
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Bit Position Value (H) Description (Continued) 0 Input Capture Event – INCAP 0 Previous timer interrupt is not a result of a timer input capture event. 1 Previous timer interrupt is a result of a timer input capture event. Timer ...
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Bit Position Value (H) Description (Continued) 6 Timer Input/Output Polarity – TPOL This bit is a function of the current operating mode of the timer. It deter- mines the polarity of the input and/or output signal. When the timer is ...
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Bit Position Value (H) Description (Continued) [5–3] PRES The timer input clock is divided by 2 The prescaler is reset each time the timer is disabled. This ensures proper clock division each time the timer is restarted. 000 Divide by ...
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Bit Position Value (H) Description (Continued) TMODE[2:0] 2:0 This field, along with the TMODE[3] bit in T0CTL0 register, determines the operating mode of the timer. TMODE[3:0] selects from the following modes: 0000 ONE-SHOT mode 0001 CONTINUOUS mode 0010 COUNTER ...
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Multi-Channel PWM Timer The Z16FMC includes a Multi-Channel PWM optimized for motor control applications. The PWM includes the following features: Six independent PWM outputs or three complementary PWM output pairs. • Programmable deadband insertion for complementary output pairs. • Edge-aligned ...
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Counter with Prescaler PWM Deadband Data Bus System Clock Operation PWM Option Bits To protect the configuration of critical PWM parameters, settings to enable output chan- nels and the default off-state are maintained as user option bits. These values ...
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PWM Output Polarity and Off-State The default off-state and polarity of the PWM outputs are controlled by the option bits PWMHI and PWMLO. The PWMHI option controls the off-state and polarity for PWM high-side outputs PWMH0, PWMH1 and PWMH2. The ...
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PWM output. The following sections describe the PWM TIMER modes and the registers controlling the duty-cycle and deadband time. PWMxH No Dead Band PWMLx PWMHx Dead Band Insertion PWMLx PWMHx No Dead Band PWMLx ...
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EDGE-ALIGNED Mode In EDGE-ALIGNED PWM mode, a 12-bit up counter creates the PWM period with a minimum resolution equal to the PWM clock source period. The counter counts up to the Reload value, resets to Edge-Aligned PWM Mode Period CENTER-ALIGNED ...
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POLx causes the high-side output to start in the off-state and the low-side output to start in the on-state. Manual Off-state Control of PWM Output Channels Each PWM output is controlled directly by the modulator logic or set to the ...
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PWMMPF where T minPulseOut Synchronization of PWM and ADC The ADC on the Z16FMC is synchronized with the PWM period. Enabling the PWM ADC trigger causes the PWM to generate an ADC conversion signal at the end of ...
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When a fault is detected and the PWM outputs are disabled, modulator control of the PWM outputs are reenabled either by the software or by the fault input signal deasserting. Selection of the reenable method is made using the PWM ...
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It is not recommended to write to the PWM high and low byte registers when the PWM is enabled. There are no temporary holding registers for Write operations, so simul- taneous 12-bit writes are not possible. When either the ...
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Edge-Aligned PWM Mode Period Center-Aligned PWM Mode Period Table 54. PWM Reload High Byte Register (PWMRH) Bits 7 6 Field Reserved RESET R/W R/W ADDR Bits Description 7:4 These bits are reserved. 3:0 PWMRH – Reload Register High Byte PWMRH ...
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PWM 0–2 Duty Cycle High and Low Byte Registers The PWM 0–2 H/L (High side/Low side) duty cycle high and low byte (PWMxDH and PWMxDL) registers (see Tables 56 and 57) set the duty cycle of the PWM signal. This ...
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PWM Control 0 Register The PWM Control 0 Register (PWMCTL0) controls PWM operation. Table 58. PWM Control 0 Register (PWMCTL0) Bits 7 6 Field PWMOFF OUTCTL RESET 0 0 R/W R/W R/W ADDR Bit Position Value (H) Description [7] Place ...
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PWM Control 1 Register The PWM Control 1 (PWMCTL1) register controls portions of PWM operation. Table 59. PWM Control 1 Register (PWMCTL1) Bits 7 6 Field RLFREQ[1:0] RESET 00 R/W R/W ADDR Bit Position Value (H) Description [7:6] Reload Event ...
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PWM Deadband Register The PWM deadband (PWMDB) register (see Table 60) stores the 8-bit PWM deadband value. The deadband value determines the number of PWM input cycles to use for the deadband time for complementary PWM output pairs. When counting ...
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PWM Fault Mask Register The PWM fault mask register, enables individual fault sources. When an input is asserted, PWM behavior is determined by the <CrossRef>PWM Fault Control Register (PWM- FCTL). The PWM Fault Mask (PWMF) the Comparator 0-3 outputs generate ...
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PWM Fault Status Register The PWM fault status (PWMFSTAT) register provides status of fault inputs and timer reload. The fault flags indicate the fault source, which is active fault source is masked, the flag in this register is ...
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PWM Fault Control Register The PWM fault control (PWMFCTL) register (see Table 64), determines how the PWM recovers from a fault condition. Settings in this register select automatic or software con- trolled PWM restart. Table 64. PWM Fault Control Register ...
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Bit Position Value (H) Description [1] Fault 0 Interrupt Fault0INT 0 Interrupt on fault 0 pin assertion disabled. 1 Interrupt on Fault0 pin assertion enabled. [0] Fault 0 Restart Fault0RST 0 Automatic recovery. PWM resumes control of outputs when all ...
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Table 66. PWM Output Control Register (PWMOUT) Bits 7 6 Field Reserved Reserved RESET ADDR Bit Position Value (H) Description [7,6] Must be 0. Reserved [5, 3, 1] PWM 2L/1L/0L output configuration OUT2L/ 0 PWM ...
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Bit Position Value (H) Description [6] High Side Active enable HEN 0 Ignore Product of PWMH0, PWMH1, PWMH2 in sample/hold equation. 1 Hold when PWMH0, PWMH1, PWMH2 are all active. [5] High Side inactive enable NHEN 0 Ignore product of ...
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Watchdog Timer The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power faults and other system-level problems which place the Z16FMC device into unsuitable operating states. The WDT includes the following features: On-chip RC oscillator • A selectable ...
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Table 68. Watchdog Timer Approximate Timeout Delays WDT Reload Value WDT Reload Value (Hex) (Decimal) 0400 1024 FFFF 65,536 Watchdog Timer Refresh When enabled first, the WDT is loaded with the value in the Watchdog Timer Reload reg- isters. The ...
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WDT Reset in Normal Operation If configured to generate a Reset when a timeout occurs, the WDT forces the device into the Reset state. The WDT status bit in the more information about Reset and the WDT status bit, see ...
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Reading from these regis- ters returns the current WDT count value. The 16-bit WDT Reload Value must not be set to a value less than Caution: Table 69. Watchdog Timer Reload ...
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LIN-UART The Local Interconnect Network Universal Asynchronous Receiver/Transmitters (LIN- UART) are full-duplex communication channels capable of handling asynchronous data transfers in standard UART applications as well as providing LIN protocol support. Features of the LIN-UARTs include: 8-bit asynchronous data transfer ...
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Parity Checker Receive Shifter RxD Receive Data Transmit Data Register Transmit Shift Register TxD Parity Generator CTS DE Operation Data Format for Standard UART Modes The LIN-UART always transmits and receives data in an 8-bit data format with the first ...
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High stop bits. Figures 15 and 16 display the asynchronous data format employed by the LIN-UART without parity and with parity, respectively. Idle State of Line lsb 1 Start Bit0 0 Figure 15. ...
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Set or clear the using the CTS pin. 5. Check the TDRE data register is empty (indicated by a 1). If this register is empty, continue to Step 6. If the transmit data register is full (indicated by a ...
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Execute an EI The LIN-UART is now configured for interrupt-driven data transmission. As the LIN- UART transmit data register is empty, an interrupt is generated immediately. When the LIN-UART transmit interrupt is detected and there is transmit data ready ...
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Read data from the LIN-UART receive data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions are required depending on the MULTIPROCESSOR mode bits 7. Return to Step 5 to receive additional data. Receiving Data using the Interrupt-Driven Method ...
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Check the LIN-UART Status 0 register to determine whether the source of the inter- rupt is error, break, or received data the interrupt was due to data available, read the data from the LIN-UART receive data register. ...
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DE 0 Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 17. LIN-UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) The DE to Start bit setup time is calculated as follows: 1 ...
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Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 18. LIN-UART Asynchronous MULTIPROCESSOR Mode Data Format In MULTIPROCESSOR (9-bit) mode, the MULTIPROCESSOR control bit. The LIN-UART Control 1 and Status 1 registers provide MULTIPROCESSOR (9-bit) mode control and ...
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If the new frame’s address matches the LIN-UART’s, then the data in the new frame is processed. The second scheme is enabled by setting address into the LIN-UART address compare register. This mode introduces more ...
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Parity error (PE bit in Status0 register) is redefined as the Physical Layer Error (PLE) • bit. The PLE bit indicates that receive data does not match transmit data when the LIN- UART is transmitting. This applies to both MASTER ...
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In the LIN SLAVE mode, the LinState field is updated by hardware as the slave moves through the Wait for Break, AutoBaud and Active states. The noise filter is also required to be enabled and configured when interfacing to ...
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LIN-UART is placed (by software) into either Lin Master or Lin Slave Wait for Break states as appropriate. If the break duration exceeds fifteen bit times, the RxBreakLength Lin Sleep state ...
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Transmitter Interrupts The transmitter generates a single interrupt when the transmit data register empty bit ( ) is set to 1. This indicates that the transmitter is ready to accept new data for trans- TDRE mission. The TDRE interrupt occurs ...
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In LIN mode, an overrun error is signaled for receive data overruns as described above and in the LIN Slave, if the BRG counter overflows during the autobaud sequence (the bit will also be set in this case). There is ...
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Baud Rate Generator Interrupts If the BRGCTL bit of the Multiprocessor Control Register is set (see page 132) and the bit of the Control 0 Register is 0, the LIN-UART receiver interrupt asserts when the REN LIN-UART baud rate generator ...
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Load the appropriate 16-bit count value into the LIN-UART baud rate high and low byte registers. 3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in the LIN-UART Control1 register to 1. Enable the ...
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System Clock NFEN, NFCTL LIN-UART Figure 20. Noise Filter System Block Diagram Operation Figure 21 displays the operation of the noise filter with and without noise. The noise filter in this example is a 2-bit up/down counter, which saturates at ...
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Sample Clock Input RxD (ideal) Noise Filter Up/Dn Cntr ...
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Table 71. LIN-UART Transmit Data Register (UxTXD) Bits 7 6 Field RESET R/W ADDR Bits Description 7:0 TXD – Transmit Data LIN-UART transmitter data byte to be shifted out through the TXD pin. LIN-UART Receive Data Register Data bytes received ...
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Table 73. LIN-UART Status 0 Register – Standard UART Mode (UxSTAT0) Bits 7 6 Field RDA PE RESET ADDR Bits Description 7 RDA – Receive Data Available This bit indicates that the LIN-UART receive data ...
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Bits Description (Continued) 0 CTS – CTS signal When this bit is read it returns the CTS signal level. If LBEN = 1, the CTS input signal is replaced by the internal receive data Available signal to provide flow control ...
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Bits Description (Continued) 3 BRKD – Break Detect This bit is set in LIN mode if (a) in LinSleep state and a break of at least 4 bit times occurred (Wake-up event) or (b) in Slave Wait Break state and ...
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Bits Description (Continued) 4:0 Mode Status This read-only field returns status corresponding to the mode selected by MSEL as follows: 000: MULTIPROCESSOR and NORMAL UART mode status = {NE NEWFRM, MPRX} 001: Noise filter status = {NE, 0,0,0,0} ...
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Hardware Revision Mode Status Field (MSEL = 111B) This field indicates the hardware revision of the LIN-UART block. 00_xxx LIN UART hardware rev 01_xxx Reserved 10_xxx Reserved 11_xxx Reserved LIN-UART Control 0 Register The LIN-UART Control 0 register (see Table ...
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Bits Description (Continued) 2 SBRK – Send Break This bit pauses or breaks data transmission. Sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending data before setting this bit. In standard UART mode, ...
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Bits Description 7,5 MPMD[1:0] – MULTIPROCESSOR Mode If MULTIPROCESSOR (9-bit) mode is enabled The LIN-UART generates an interrupt request on all received bytes (data and address The LIN-UART generates an interrupt request only on received address ...
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Noise Filter Control Register (LIN-UART Control1 Register with MSEL = 001b). When = MSEL 001b Table 78. Noise Filter Control Register (UxCTL1 with MSEL = 001b) Bits 7 6 Field NFEN RESET 0 0 R/W R/W R/W ADDR Bits Description ...
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LIN Control Register (LIN-UART Control1 Register with MSEL = 010b) When = MSEL 010b Table 79. LIN Control Register (UxCTL1 with MSEL = 010b) Bits 7 6 Field LMST LSLV RESET 0 0 R/W R/W R/W ADDR Bits Description 7 ...
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LIN-UART Address Compare Register The LIN-UART address compare register stores the multi-node network address of the LIN-UART. When the address bytes are compared to the value stored in the address compare register. Receive interrupts and RDA Table 80. LIN-UART Address ...
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The LIN-UART data rate is calculated using the following equation for standard UART modes. For LIN protocol, the baud rate registers must be programmed with the baud period rather than 1/16 baud period. The UART must be disabled when updating ...
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When the LIN-UART is disabled, the baud rate generator functions as a basic 16-bit timer with interrupt on timeout. To configure the baud rate generator as a timer with interrupt on timeout, complete the following procedure: 1. Disable the LIN-UART ...
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Table 83. LIN-UART Baud Rates (Continued) 5.5296 MHz System Clock Desired Rate BRG Divisor Actual Rate (kHz) (Decimal) (kHz) 1250.0 N/A N/A 625.0 N/A N/A 250.0 1 345.6 115.2 3 115.2 57.6 6 57.6 38.4 9 38.4 19.2 18 19.2 ...
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... UART. Communication is half-duplex, which means that simultaneous data transmission and reception is not allowed. PS028702-1210 Z16FMC Series Motor Control MCUs RxD Infrared TxD Encoder/Decoder Baud Rate (Endec) Clock Product Specification ® Zilog ZHX1810 RXD RXD TXD TXD Infrared Transceiver Infrared Encoder/Decoder 141 ...
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The baud rate is set by the UART’s baud rate generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to ...
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Receiving IrDA Data Data received from the infrared transceiver via the IR_RXD signal through the RXD pin is decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is used by the infrared endec to ...
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If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for the next falling edge. As each falling edge is detected, the Endec clock coun- ter is reset, resynchronizing the ...
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Enhanced Serial Peripheral Interface The Enhanced Serial Peripheral Interface (ESPI) supports SPI (Serial Peripheral Interface) and Inter IC Sound (I The features of the ESPI include: Full-duplex, synchronous, character-oriented communication • Four-wire interface (SS, SCK, MOSI, MISO) • Transmit and ...
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Peripheral Bus ESPI Control ESPI Status Register Register ESPI State ESPI Mode Register Register ESPI State Machine SS out SS in MISO MOSI PS028702-1210 Z16FMC Series Motor Control MCUs ESPI BRH Register ESPI BRL Register Baud Generator ...
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ESPI Signals The four ESPI signals are: Master-In/Slave-Out (MISO) • Master-Out/Slave-In (MOSI) • Serial clock (SCK) • Slave select (SS) • The following paragraphs describe these signals in both MASTER and SLAVE modes. The appropriate GPIO pins must be ...
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Slave Select The SS signal is a bidirectional framing signal with several modes of operation to support SPI and other synchronous serial interface protocols. The SLAVE SELECT mode is selected by the SSMD field of the ESPI mode register. The ...
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STR bit on the SPI module replaced with ESPIEN1; SPIEN replaced by – ESPIEN0; these enhancements allow unidirectional transfers, which minimize software or DMA overhead BIRQ replaced with BRGCTL – Mode register: • Added SSMD field which adds support for ...
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The TDRE and RDRF signals also generate transmit and receive DMA requests. In many cases the software application is only moving information in one direction. In such a case, either the TDRE or RDRF interrupts/DMA ...
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Transfer Format with Phase Equals Zero Figure 26 displays the timing diagram for an SPI type transfer in which PHASE = SPI transfers the clock only toggles during the character transfer. The two SCK wave- forms show polarity with CLKPOL ...
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SCK (CLKPOL = 0) SCK (CLKPOL = 1) MOSI MISO Input Sample Time SS Figure 27. ESPI Timing when Modes of Operation This section describes the different modes of data transfer supported by the ESPI block. The mode is selected ...
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DMA request is being serviced (set TEOF before or simultaneously with writing the final data byte). When the final bit of the final character is transmitted, the hardware will automatically deassert the SSV and TEOF bits. The second method ...
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SCK (SSMD = 00, PHASE = 0, CLKPOL = 0, SSPO = 0) Bit0 MOSI, MISO Rx Data Register Data Register Shift Register Tx/Rx n–1 TDRE RDRF ESPI Interrupt Mode Inter-Integrated Circuit Sound mode ...
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NUMBITS to a value other than 0. Example To send 20 bits/frame, set NUMBITS = 5 and read/write 4 bytes per frame. ...
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SSIO bit must still be set single master system. Figure 30 and Figure 31 displays the ESPI block configured as an SPI master. To Slave’s SS Pin From Slave To Slave ...
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The master asserts the SS pin on the selected slave. Then, the active master drives the clock and transmit data on the SCK and MOSI pins to ...
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Error Detection Error events detected by the ESPI block are described in this section. Error events gener- ate an ESPI interrupt and set a bit in the ESPI status register. The error bits of the ESPI Status Register are read/write ...
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SS is asserted and between the previous SCK edge and SS deassertion. A timeout indicates the master is stalled or disabled. Writing 1 to ABT clears this error flag. ESPI Interrupts ESPI has a single interrupt output which is ...
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For a slave, all options are valid. When a slave is operating in receive only mode, it will transmit characters of all 1s. DMA Descriptors For ESPI Transmit DMA descriptors, the ...
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SPI Baud Rate (bps) Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value 65536 = 131072). When the ESPI is disabled, the BRG functions as a basic 16-bit timer with interrupt ...
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Writes to the ESPI Data Register load the Transmit Data Register unless final bit received resides in bit position 0. With the ESPI configured as a Master, writing a ...
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Bits Description 7:2 Reserved These bits are reserved. 1 TEOF – Transmit End Of Frame This bit is used in Master mode to indicate that the data in the transmit data register is the final byte of the transfer or ...
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Bits Description (Continued) 6,0 ESPIEN1, ESPIEN0 – ESPI Enable and Direction Control 00 = ESPI block is disabled. BRG is used as a general purpose timer by setting BRGCTL = RECEIVE ONLY Mode. Use this setting if ...
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ESPI Mode Register The ESPI Mode Register (see Table 92) configures the character bit width and mode of the ESPI IO pins. Table 92. ESPI Mode Register (ESPIMODE) Bits 7 6 Field SSMD RESET 000 R/W R/W ADDR Bits Description ...
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Bits Description (Continued) 4:2 NUMBITS[2:0] – Number of Data Bits Per Character to Transfer This field contains the number of bits to shift for each character transfer. For information about valid bit positions when the character length is less than ...
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Bits Description (Continued) 6 TUND – Transmit Underrun Transmit Underrun error has not occurred Transmit Underrun error has occurred. 5 COL – Collision Multi-Master collision (mode fault) has not occurred. 1 ...
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Bits Description 7 SCKI – Serial Clock Input This bit reflects the state of the serial clock pin The SCK input pin is Low 1 = The SCK input pin is High 6 SDI – Serial Data Input ...
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Table 95. ESPISTATE Values and Description (Continued) ESPISTATE Value 10_0101 10_0010 10_0011 10_0000 10_0001 ESPI Baud Rate High and Low Byte Registers The ESPI Baud Rate High and Low Byte registers (see Tables 96 and 97) combine to form a ...
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Table 96. ESPI Baud Rate High Byte Register (ESPIBRH) Bits 7 6 Field RESET 1 1 R/W R/W R/W ADDR Bits Description 7:0 BRH = ESPI Baud Rate High Byte Most significant byte, BRG[15:8], of the ESPI Baud Rate Generator’s ...
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I C Master/Slave Controller 2 The I C Master/Slave Controller makes the Z16FMC bus compatible with the I 2 col. The I C bus consists of the serial data signal (SDA) and a serial clock (SCL) signal bidirectional lines. ...
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I2CISTAT Interrupt Tx and Rx DMA Requests Figure 33 Master/Slave Controller Registers Table 98 summarizes the I PS028702-1210 Z16FMC Series Motor Control MCUs SDA SCL Baud Rate Generator I2CBRH I2CBRL Tx/Rx State Machine ...
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Table 98 Master/Slave Controller Registers Name Abbreviation Data I2CDATA Interrupt Status I2CISTAT Control I2CCTL Baud Rate High I2CBRH Baud Rate Low I2CBRL ...
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Operation 2 The I C Master/Slave Controller operates in either SLAVE-ONLY mode or MASTER/ SLAVE mode with Master arbitration. In MASTER/SLAVE mode used as the only Master on the bus or as one of several Masters on the ...
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Transmit Interrupts Transmit interrupts ( The transmit data register is empty and the • 2 The I C Controller is enabled, with any one of the following: • The first bit of a 10-bit address is shifted out – The ...
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I C Controller switches to SLAVE mode when this occurs. This bit clears automatically when the I2CISTAT Register is read. Stop/Restart Interrupts A Stop/Restart event interrupt ( is in SLAVE mode and a Stop or Restart condition is received, ...
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Software Control The I C Controller is configured using the I field of the I MODE[1:0] ter/Slave or Slave only mode and configures the slave for 7-bit or 10-bit addressing recog- nition. The baud rate High and ...
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Slaves) or during the data phase when the Masters are attempting to write different data to the same Slave. When a Master loses arbitration, software is informed by means of the Arbitration Lost interrupt. Software repeats the ...