Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 280

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Baud Rate Generator
After the receiver has sampled the final data bit, it waits one full bit time and sample the
middle of the stop bit. If the stop bit is Low, the receiver detects a framing error.
If the stop bit is High, the data was correctly framed between a start and stop bit. After the
receiver samples the middle of the stop bit, it begins searching for another start bit. The
receiver does not wait for the full stop bit to be received before searching for the next start
bit, in effect correcting for any bit skew due to error between the transmit and receive baud
rate clocks.
The baud rate generator (BRG) is used to generate a bit clock for transmit and receive
operations. The BRG reload register is automatically configured by the auto-baud 
detector, or it is written by software.
The value in the BRG reload register is calculated as:
BAUD RELOAD VALUE =
This reload value is the number of system clocks used to transmit and receive eight data
bits.
The BRG has a 16-bit reload counter and is clocked by the system clock. When the OCD
is enabled, this register is limited to 12 bits. The minimum baud rate is calculated using the
following equation:
BAUD RELOAD VALUE =
The minimum baud rate when the OCD is enabled is the system clock frequency divided
by 512. The minimum baud rate is the system clock frequency divided by 8192 when the
OCD is disabled.
For asynchronous operation, the maximum baud rate is roughly the system clock fre-
quency divided by eight (eight clocks per bit). With slow baud rates and clean signals, you
will be able to achieve asynchronous baud rates up to 4 clocks per bit. If data is synchro-
nized with the system clock, the maximum baud rate is the system clock frequency (one
bit per clock). The maximum baud rates are limited by the rise and fall times due to the
cable impedance. Table 151 lists minimum and maximum baud rates for sample crystal
frequencies.
P R E L I M I N A R Y
SYSTEM CLOCK
SYSTEM CLOCK
BAUD RATE
BAUD RATE
Z16FMC Series Motor Control MCUs
x 8
x 8
Product Specification
On-Chip Debugger
258