Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 113

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PWM Control Register Definitions
PS028702-1210
PWM Operation in CPU HALT Mode
PWM Operation in CPU STOP Mode
Observing the State of PWM Output Channels
PWM High and Low Byte Registers
When a fault is detected and the PWM outputs are disabled, modulator control of the
PWM outputs are reenabled either by the software or by the fault input signal deasserting.
Selection of the reenable method is made using the PWM Fault Control Register (PWM-
FCTL). Configuration of the fault modes and reenable methods allow pulse-by-pulse lim-
iting and hard shutdown. When configured in AUTOMATIC RESTART mode, the PWM
outputs are reengaged at beginning of the next PWM cycle (master timer value is equal to
0) if all fault signals are deasserted. In software controlled restart, all fault inputs must be
deasserted and the fault flags must be cleared.
The fault input pin is Schmitt-triggered. The input signal from the pin as well as the com-
parators pass though an analog filter to reject high-frequency noise.
The logic path from the fault sources to the PWM output is asynchronous ensuring that the
fault inputs forces the PWM outputs to their off-state even if the system clock is stopped.
When the CPU is operating in HALT mode, the PWM continues to operate if it is enabled.
To minimize current in HALT mode, the PWM must be disabled by clearing the PWMEN
bit to 0.
When the CPU is operating in STOP mode, the PWM is disabled as the system clock
ceases to operate in STOP mode. The PWM output remains in the same state as they were
prior to entering the STOP mode. In normal operation, the PWM outputs must be disabled
by software prior to the CPU entering the STOP mode. A fault condition detected in STOP
mode forces the PWM outputs to the predefined off-state.
The logic value of the PWM outputs is sampled by reading the PWMIN Register. If a
PWM channel pair is disabled (option bit is not set), the associated PWM outputs are
forced to high impedance and are used as general purpose inputs.
The following sections describe the various PWM control registers.
The PWM high and low byte (PWMH and PWML) registers (see Tables 52 and 53) con-
tain the current 12-bit PWM count value. Reads from PWMH stores the value in PWML
to a temporary holding register. A read from PWML always returns this temporary register
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Multi-Channel PWM Timer
Product Specification
91