Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 156

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Bits
7,5
6
4
3
2
1
0
Description
MPMD[1:0] – MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The LIN-UART generates an interrupt request on all received bytes (data and address).
01 = The LIN-UART generates an interrupt request only on received address bytes.
10 = The LIN-UART generates an interrupt request when a received address byte matches the
value stored in the address compare register and on all successive data bytes until an address
mismatch occurs.
11 = The LIN-UART generates an interrupt request on all received data bytes for which the
most recent address byte matched the value in the address compare register.
MPEN – MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) mode.
0 = Disable MULTIPROCESSOR (9-bit) mode.
1 = Enable MULTIPROCESSOR (9-bit) mode.
MPBT – Multiprocessor Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled.
0 = Send 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send 1 in the multiprocessor bit location of the data stream (9th bit).
DEPOL – Driver Enable Polarity
0 = DE signal is active High.
1 = DE signal is active Low.
BRGCTL – Baud Rate Generator Control
This bit causes different LIN-UART behavior depending on whether the LIN-UART receiver is
enabled (REN = 1 in the LIN-UART Control 0 Register).
When the LIN-UART receiver is not enabled, this bit determines whether the baud rate genera-
tor issues interrupts.
0 = BRG is disabled. Reads from the baud rate high and low byte registers return the BRG
Reload Value.
1 = BRG is enabled and counting. The BRG generates a receive interrupt when it counts down
to 0. Reads from the baud rate high and low byte registers return the current BRG count value.
When the LIN-UART receiver is enabled, this bit allows reads from the baud rate registers to
return the BRG count value instead of the Reload Value.
0 = Reads from the baud rate high and low byte registers return the BRG Reload Value.
1 = Reads from the baud rate high and low byte registers return the current BRG count value.
Unlike the timers, there is no mechanism to latch the High byte when the Low byte is read.
RDAIRQ – Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the interrupt controller.
1 = Received data does not generate an interrupt request to the interrupt controller. Only
receiver errors generate an interrupt request.
IREN – Infrared Encoder/Decoder Enable
0 = Infrared encoder/decoder is disabled. LIN-UART operates normally.
1 = Infrared encoder/decoder is enabled. The LIN-UART transmits and receives data through
the Infrared encoder/decoder.
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Product Specification
LIN-UART
134