Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 218

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Bits
7
6
5
4
3
2
1
0
Description
TDRE – Transmit data register empty
When the I
I
the reception of a byte or when shifting an address and the RD bit is set. This bit clears by writ-
ing to the I2CDATA Register.
RDRF – Receive data register full
This bit is set = 1 when the I
of data. When asserted, this bit causes the I
clears by reading the I2CDATA Register.
SAM – Slave address match
This bit is set = 1 if the I
which matches the unique slave address or General Call Address (if enabled by the GCE bit in
the I
on both address bytes. When this bit is set, the RD and GCA bits are also valid. This bit clears
by reading the I2CISTAT register.
GCA – General call address
This bit is set in Slave mode when the General Call Address or START byte is recognized (in
either 7- or 10-bit Slave mode). The GCE bit in the I
recognition of the General Call Address and START byte. This bit clears when IEN = 0 and is
updated following the first address byte of each Slave mode transaction. A General Call
Address is distinguished from a START byte by the value of the RD bit (RD = 0 for General Call
Address, 1 for START byte).
RD – Read
This bit indicates the direction of transfer of the data. It is set when the Master is reading data
from the Slave. This bit matches the least-significant bit of the address byte after the START
condition occurs (for both Master and Slave modes). This bit clears when IEN = 0 and is
updated following the first address byte of each transaction.
ARBLST – Arbitration lost
This bit is set when the I
a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the I2CISTAT register is
read.
SPRS – Stop/Restart condition interrupt
This bit is set when the I
RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT register is read. Read the RSTR bit of the I2CSTATE register to determine whether
the interrupt was caused by a STOP or RESTART condition.
NCKI – NAK interrupt
In Master mode, this bit is set when a Not Acknowledge condition is received or sent and nei-
ther the START nor the STOP bit is active. In Master mode, this bit is cleared only by setting the
START or STOP bits. In Slave mode, this bit is set when a Not Acknowledge condition is
received (Master reading data from Slave), indicating the Master is finished reading. A STOP
or RESTART condition follows. In Slave mode this bit clears when the I2CISTAT register is
read.
2
C Controller generates an interrupt, except when the I
2
C Mode Register). In 10-bit addressing mode, this bit is not set until a match is achieved
2
C Controller is enabled, this bit is 1 if the I
2
2
2
C Controller is enabled in Slave mode and an address is received
C Controller is enabled in Master mode and loses arbitration (outputs
C Controller is enabled in Slave mode and detects a STOP or
2
C Controller is enabled and the I
P R E L I M I N A R Y
2
C Controller to generate an interrupt. This bit
2
C Mode Register must be set to enable
Z16FMC Series Motor Control MCUs
2
C Data Register is empty. When set, the
2
C Controller is shifting in data during
2
C Controller has received a byte
I2C Master/Slave Controller
Product Specification
196