Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 284

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Debug Lock
Error Reset
Internal
System Reset
Debug Reset
Debug Pin
Reset Pin
The interface has a locking mechanism to prevent user code from disabling the OCD and
using the DBG pin as a UART or GPIO pin. The
prevents you from disabling the OCD and modifying any register that would inhibit com-
munication with the OCD. The default state of the
DBGUART
To use the DBG pin as a UART or GPIO pin, you must program the
zero so the
unlocked, software then clears the
GPIO pin.
If the
locked before the code can disable the OCD. This locking occurs upon initializing the
Debugger during reset and writing the
The serial interface has an Auto-Reset mechanism that resets the serial interface when a
Transmit Collision or Receive Framing Error is detected. When a Transmit Collision or
Receive Framing Error is detected when
rently in progress, transmits a Serial Break condition for 4096 system clocks and sets the
ABSRCH
error.
DBGUART
bit in the DBGCTL register. This break is sent to ensure the host also detects the
option bit.
OCDLOCK
Reset Timeout
option bit is cleared and the
Figure 57. Initialization during Reset
control bit is cleared after reset. After the control register is
P R E L I M I N A R Y
OCDEN
OCDLOCK
OCDEN
control bit to use the DBG pin as a UART or
80H
Reset Pin Remains Asserted
OCDLOCK
Z16FMC Series Motor Control MCUs
is set, the OCD aborts any command cur-
control bit to 1.
DBGLOCK
DBGLOCK
00H
control bit is not set, the
IDH
bit in the DBGCTL register
bit is set accordingly to the
Product Specification
IDL
DBGUART
On-Chip Debugger
option bit to
OCD
is still
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