Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 110

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
PWM Duty Cycle Registers
Independent and Complementary PWM Outputs
Center-Aligned PWM Mode Period
EDGE-ALIGNED Mode
In EDGE-ALIGNED PWM mode, a 12-bit up counter creates the PWM period with a
minimum resolution equal to the PWM clock source period. The counter counts up to the
Reload value, resets to
Edge-Aligned PWM Mode Period
CENTER-ALIGNED Mode
In CENTER-ALIGNED PWM mode, a 12-bit up/down counter creates the PWM period
with a minimum resolution equal to twice the PWM clock source period. The counter
counts up to the Reload value and then counts down to 0.
The PWM duty cycle registers (PWMH0D, PWML0D, PWMH1D, PWML1D,
PWMH2D, PWML2D) contain a 16-bit signed value where bit 15 is the sign bit. The duty
cycle value is compared to the current 12-bit unsigned PWM count value. If the PWM
duty cycle value is set less than or equal to 0, the PWM output is deasserted for full PWM
period. If the PWM duty cycle value is set to a value greater than the PWM Reload value,
the PWM output is asserted for full PWM period.
The six PWM outputs are configured to operate independently or as three complementary
pairs. Operation as six independent PWM channels are enabled by setting the INDEN bit
in the PWM Control 1 Register (PWMCTL1). In INDEPENDENT mode, each PWM out-
put uses its own PWM duty cycle value.
When PWM outputs are configured to operate as three complementary pairs, the PWM
duty cycle values PWMH0D, PWMH1D and PWMH2D control the modulator output. In
COMPLEMENTARY OUTPUT mode deadband time is also inserted.
The POLx bits in the <CrossRef>PWM Control 1 Register (PWMCTL1) select the rela-
tive polarity of the high- and low-side signals. As illustrated in Figures 12 and 13, when
the POLx bits are cleared to 0, the PWM high-side output will start in the on-state and
transits to the off-state when the PWM timer count reaches the programmed duty cycle.
The low-side PWM value starts in the off-state and transits to the on-state as the PWM
timer count reaches the value in the associated duty cycle register. Alternately, setting the
000H
P R E L I M I N A R Y
and then resumes counting.
=
=
Prescaler
------------------------------------------------------------ -
2 Prescaler
--------------------------------------------------------------------- -

Z16FMC Series Motor Control MCUs
f
PWMclk

Reload Value
f
PWMclk

Reload Value
Multi-Channel PWM Timer
Product Specification
88