Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 213

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
3. The Master sends the second address byte. The Slave mode I
4. Software responds to the Slave Address Match interrupt by reading the I2CISTAT
5. The Master notifies the Acknowledge and sends a Restart instruction, followed by the
6. Software responds to the interrupt by reading the I2CISTAT register, clearing the
7. The Master starts the data transfer by asserting SCL Low. After the I
8. When the first bit of the first data byte is transferred, the I
9. Software responds to the transmit data interrupt by loading the next data byte into the
10. The I
11. The bus cycles through steps 7–10 until the final byte has been transferred. If software
12. Software responds to the NAK interrupt by clearing the
13. When the Master has completed the acknowledge cycle of the final transfer it asserts
14. The Slave I
the second address byte with the value in
the I2CISTAT register is set = 1, causing a Slave Address Match interrupt. The
is set = 0, indicating a write to the Slave. If a match occurs, the I
acknowledges on the I
register which clears the
first address byte with the R/W = 1. The Slave mode I
Restart followed by the first address byte with a match to
R/W = 1 (Master reads from Slave). The Slave I
I2CISTAT register, which causes the Slave Address Match interrupt. The
= 1. The Slave mode I
bit. Software loads the initial data byte into the I2CDATA Register and sets the
in the I2CCTL register.
data available to transmit the SCL is released and the Master proceeds to shift the first
data byte.
bit, which asserts the transmit data interrupt.
I2CDATA Register.
Acknowledge (or Not Acknowledge for the final data byte).
has not yet loaded the next data byte when the Master brings SCL Low to transfer the
most significant data bit, the Slave I
register is written.
When the Slave receives a Not Acknowledge, the I
the I2CISTAT register and generates the NAK interrupt.
register and by asserting the
the STOP or RESTART condition on the bus.
I2CISTAT register).
2
C Master shifts in the remainder of the data byte. The Master transmits the
2
C Controller asserts the STOP/RESTART interrupt (set
2
2
P R E L I M I N A R Y
C Controller acknowledges on the bus.
C bus, indicating that it is available to accept the data.
SAM
FLUSH
bit. When the
2
bit of the I2CCTL register.
C Controller holds SCL Low until the data
SLA
Z16FMC Series Motor Control MCUs
RD
[7:0]. If there is a match, the
bit = 0, no further action is required.
2
C Controller sets the
2
C Controller sets the
2
C Controller recognizes the
TXI
SLA
2
I2C Master/Slave Controller
C controller sets the
Product Specification
2
bit in the I2CCTL
C Controller compares
[9:8] and detects the 
2
C Controller
2
SPRS
C Controller has
SAM
NCKI
RD
SAM
bit in
bit in the
bit is set
TXI
bit in
RD
bit in
TDRE
SAM
bit
bit
191