Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 101

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Bit Position
6:5
4
3:1
Value (H) Description (Continued)
000
001
010
100
101
011
110
111
0
1
Timer Interrupt Configuration – TICONFIG
This field configures timer interrupt definitions. These bits affect all modes.
The effect per mode is explained below:
ONE SHOT, CONTINUOUS, COUNTER, PWM, COMPARE, DUAL PWM,
TRIGGERED ONE-SHOT, COMPARATOR COUNTER:
0x Timer interrupt occurs on reload.
10 Timer interrupts are disabled.
11 Timer Interrupt occurs on reload.
GATED:
0x Timer interrupt occurs on reload.
10 Timer interrupt occurs on inactive gate edge.
11 Timer interrupt occurs on reload.
CAPTURE, CAPTURE/COMPARE, CAPTURE RESTART:
0x Timer interrupt occurs on reload and capture.
10 Timer interrupt occurs on capture only.
11 Timer interrupt occurs on reload only.
Timer Cascade – CASCADE
This field allows the timers to be cascaded for larger counts. Only Counter
Mode must be used with this feature.
The timer is not cascaded.
Timer is cascaded. If timer 0 CASCADE bit is set, ANALOG COMPARATOR
output is used as input. If timer 1 CASCADE bit is set, the Timer 0 output is
used as the input. If timer 2 CASCADE bit is set, the timer 1 output is used as
input.
PWM Delay Value – PWMD
This field is a programmable delay to control the number of additional system
clock cycles following a PWM or Reload compare before the timer output or
the timer output complement is switched to the active state. This field ensures
a time gap between deassertion of one PWM output to the assertion of its
complement.
No delay.
2 cycles delay.
4 cycles delay.
8 cycles delay.
16 cycles delay.
32 cycles delay.
64 cycles delay.
128 cycles delay.
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Product Specification
Timers
79