Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 174

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Modes of Operation
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
This section describes the different modes of data transfer supported by the ESPI block.
The mode is selected by the slave select mode (SSMD) field of the mode register.
SPI Mode
This mode is selected by setting the SSMD field of the mode Register to 000. In this
mode, software or DMA controls the assertion of the SS signal directly via the SSV bit of
the SPI transmit data command register. Either DMA or software is used to control an SPI
mode transaction. Prior to or simultaneously with writing the first transmit data byte, soft-
ware or DMA sets the SSV bit. Software sets the SSV bit either by performing a byte write
to the transmit data command register prior to writing the first transmit character to the
data register or by performing a word write to the data register address which loads the
first transmit character and simultaneously sets the SSV bit.
The DMA sets the SSV bit via the command field of the descriptor. The SSV bit is written
on the DMA command bus prior to or in sync with the first data byte. SS will remain
asserted while one or more characters are transferred. There are two mechanisms for deas-
serting SS at the end of the transaction. One method is used by DMA and also by software,
is to set the
MOSI
MISO
SCK
SCK
SS
TEOF
Figure 27. ESPI Timing when
bit of the transmit data command register when the final TDRE interrupt
Bit7
Bit7
Bit6
Bit6
P R E L I M I N A R Y
Bit5
Bit5
Bit4
Bit4
PHASE
Z16FMC Series Motor Control MCUs
Bit3
Bit3
Enhanced Serial Peripheral Interface
= 1
Bit2
Bit2
Product Specification
Bit1
Bit1
Bit0
Bit0
152