Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 184

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 89. ESPI Data Register (ESPIDATA)
Table 90. ESPI Transmit Data Command Register (ESPITDCR)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
7:0
Bits
Field
RESET
R/W
ADDR
ESPI Transmit Data Command Register
Description
DATA – Data
Transmit and/or receive data. Writes to the ESPIDATA Register load the shift register. Reads
from the ESPIDATA Register return the value of the receive data register.
R/W
R
X
7
7
0
tents of the shift register at the end of each transfer. Writes to the ESPI Data Register load
the Transmit Data Register unless
final bit received resides in bit position 0.
With the ESPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the ESPI configured as a Slave, writing a data byte to this register
loads the shift register in preparation for the next data transfer with the external Master. In
either the Master or Slave modes, if TDRE = 0, writes to this register are ignored.
When the character length is less than 8 bits (as set by the NUMBITS field in the ESPI
Mode Register), the transmit character must be left justified in the ESPI Data Register. A
received character of less than 8 bits is right justified (final bit received is in bit position
0). For example, if the ESPI is configured for 4-bit characters, the transmit characters must
be written to ESPIDATA[7:4] and the received characters are read from ESPIDATA[3:0].
The ESPI Transmit Data Command register (see Table 90) provides control of the SS pin
when it is configured as an output (MASTER mode). The TEOF and SSV bits are con-
trolled by the DMA interface as well as by a bus write to this register.
R/W
R
6
X
6
0
R/W
X
R
5
5
0
P R E L I M I N A R Y
R/W
TDRE = 0
R
X
4
4
0
FF_E260H
FF_E261H
DATA
. Data is shifted out starting with bit 7. The
R/W
Z16FMC Series Motor Control MCUs
X
R
3
3
0
Enhanced Serial Peripheral Interface
R/W
R
X
2
2
0
Product Specification
TEOF
R/W
R/W
X
1
1
0
SSV
R/W
R/W
X
0
0
0
162