Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 19

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
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Table 100. I2C Interrupt Status Register (I2CISTAT) . . . . . . . . . . . . . . . . . . . . . . . . 195
PWM Output Control Register (PWMOUT) . . . . . . . . . . . . . . . . . . . . . . . 102
Current-Sense Sample and Hold Control Register (CSSHR0 
and CSSHR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Watchdog Timer Approximate Timeout Delays . . . . . . . . . . . . . . . . . . . . 105
Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . 107
Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . 107
LIN-UART Transmit Data Register (UxTXD) . . . . . . . . . . . . . . . . . . . . . 127
LIN-UART Receive Data Register (UxRXD) . . . . . . . . . . . . . . . . . . . . . . 127
LIN-UART Status 0 Register – Standard UART Mode (UxSTAT0) . . . . 128
LIN-UART Status 0 Register – LIN Mode (UxSTAT0) . . . . . . . . . . . . . . 129
LIN-UART Mode Select and Status Register (UxMDSTAT) . . . . . . . . . . 130
LIN-UART Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . 132
MultiProcessor Control Register (UxCTL1 with MSEL = 000b) . . . . . . . 133
Noise Filter Control Register (UxCTL1 with MSEL = 001b) . . . . . . . . . . 135
LIN Control Register (UxCTL1 with MSEL = 010b) . . . . . . . . . . . . . . . . 136
LIN-UART Address Compare Register (UxADDR) . . . . . . . . . . . . . . . . . 137
LIN-UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . 137
LIN-UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . 137
LIN-UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
ESPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
ESPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation . . 150
ESPI Tx DMA Descriptor Command Field . . . . . . . . . . . . . . . . . . . . . . . . 160
ESPI Tx DMA Descriptor Status field . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
ESPI Rx DMA Descriptor Status field . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
ESPI Data Register (ESPIDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
ESPI Transmit Data Command Register (ESPITDCR) . . . . . . . . . . . . . . . 162
ESPI Control Register (ESPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
ESPI Mode Register (ESPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
ESPI Status Register (ESPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ESPI State Register (ESPISTATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
ESPISTATE Values and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
ESPI Baud Rate High Byte Register (ESPIBRH) . . . . . . . . . . . . . . . . . . . 170
ESPI Baud Rate Low Byte Register (ESPIBRL) . . . . . . . . . . . . . . . . . . . . 170
I2C Master/Slave Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Product Specification
List of Tables
xix