Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 215

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
occurs. Software must respond to this interrupt by clearing the DMAIF bit and setting the
STOP bit to end the transaction.
Master Read Transaction with Data DMA
In master read transactions, the Master is responsible for the Acknowledge for each data
byte transferred. The Master software must set the NAK bit after the next to the final data
byte has been received or while the final byte is being received. The DMA supports this by
setting the DMA watermark to 0x01, which results in a DMA interrupt when the next to
the final byte has been received. A DMA interrupt also occurs when the final byte is
received. Otherwise, the sequence is similar to that described above for the Master write
transaction.
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•
•
•
•
•
•
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Slave Write Transaction with Data DMA
In a transaction where the I
master, the software must set the
the reception of the final byte. As in the Master Read transaction described above, the
watermark DMA interrupt is used to notify software when the N–1st byte has been
received.
Configure the selected DMA channel for I
DMACTL register for the final buffer to be transferred. Typically one buffer is defined
with a transfer length of N where N bytes are expected to be read from the slave. The
watermark is set to 1 by writing a 0x01 to DMAxLAR[23:16].
The I
error conditions. A Not Acknowledge interrupt occurs on the final byte transferred.
The I
master mode transactions. The
Initiate the I
page 178), using the
slave acknowledges. Do not set the STOP bit unless
acknowledge).
Set the
The DMA transfers the data to memory as it is received from the slave.
When the first DMA interrupt occurs indicating the (N–1)st byte has been received, the
NAK
When the second DMA interrupt occurs, it indicates that the Nth byte has been re-
ceived. Set the STOP bit in the I2CCTL register. The STOP bit is polled by software to
determine when the transaction is actually completed.
Clear the
bit must be set in the I2CCTL register.
2
2
C interrupt must be enabled in the interrupt controller to alert software of any I
C Master/Slave must be configured as defined in the sections above describing
DMAIF
DMAIF
2
C transaction as described in the
bit in the I2CMODE register.
bit in the I2CMODE register.
ACKV
P R E L I M I N A R Y
2
C Master/Slave operates as a slave receiving data written by a
and
NAK
TXI
ACK
bit after the N–1st byte has been received or during
bit in the I2CCTL register must be cleared.
bits in the I2CSTATE register to determine if the
2
Z16FMC Series Motor Control MCUs
C receive. The
Master Address Only Transactions
ACKV
=1 and
I2C Master/Slave Controller
IEOB
Product Specification
bit must be set in the
ACK
=0 (slave did not
(see
2
C
193