Z16FMC64AG20SG Zilog, Z16FMC64AG20SG Datasheet - Page 118

• Manufacturer Part Number: Z16FMC64AG20SG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 59. PWM Control 1 Register (PWMCTL1)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bit Position
[7:6]
RLFREQ[1:0]
[5]
INDEN
[4]
Pol2
[3]
Pol1
[2]
Pol0
[1:0]
PRES
PWM Control 1 Register
RLFREQ[1:0]
7
The PWM Control 1 (PWMCTL1) register controls portions of PWM operation.
Value (H)
R/W
00
01
10
11
00
01
10
11
0
1
1
0
1
0
1
0
00
6
Reload Event Frequency
This bit field is buffered. Changes to the reload event frequency takes effect
at the end of the current PWM period. Reads always return the bit values
from the temporary holding register. 
PWM reload event occurs at the end of every PWM period.
PWM reload event occurs once every two PWM periods.
PWM reload event occurs once every four PWM periods.
PWM reload event occurs once every eight PWM periods.
Independent PWM Mode Enable
PWM outputs operate as three complementary pairs.
PWM outputs operate as six independent channels.
Invert output polarity for channel pair PWM2.
Non-inverted polarity for channel pair PWM2.
Invert output polarity for channel pair PWM1.
Non-inverted polarity for channel pair PWM1.
Invert output polarity for channel pair PWM0.
Non-inverted polarity for channel pair PWM0.
PWM Prescaler
The prescaler divides down the PWM input clock (either the system clock or
the PWMIN external input). This field is buffered. Changes to this field take
effect at the next PWM reload event. Reads always return the values from
the temporary holding register.
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Description
INDEN
R/W
5
0
P R E L I M I N A R Y
Pol45
R/W
4
0
FF_E381H
Pol23
R/W
Z16FMC Series Motor Control MCUs
3
0
Pol10
R/W
2
0
Multi-Channel PWM Timer
Product Specification
1
PRES[1:0]
R/W
00
0
96