MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 993

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

See
Accessing the PCI Configuration Space,”
17.3.1.1.2
The CFG_DATA register is shown in
Table 17-5
The CFG_DATA register is a 4-byte window into the little-endian PCI configuration header data structure;
therefore, byte addressing within the CFG_DATA register uses little-endian convention. Note that
CFG_DATA may contain 1, 2, 3, or 4 bytes depending on the size of the register being accessed.
See
Accessing the PCI Configuration Space,”
17.3.1.1.3
An external PCI interrupt acknowledge transaction is generated by reading the INT_ACK register. For
PCI, INT_ACK is at offset 0x008. INT_ACK is shown in
Table 17-6
Freescale Semiconductor
Offset 0x004
Offset 0x008
Reset
Reset
Section 17.4.2.11.2, “Host Accessing the PCI Configuration Space,”
Section 17.4.2.11.2, “Host Accessing the PCI Configuration Space,”
W
W
R
R
0
0
0–31
Bits
describes the bit settings for the CFG_DATA register
describes the bit settings for the INT_ACK register.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Configuration Data Register (CFG_DATA)
PCI Interrupt Acknowledge Register (INT_ACK)
Name
Data
0–31 Data A read to this register generates a PCI interrupt acknowledge cycle.
Bits Name
A read or write to this register starts a PCI configuration cycle if the PCI CFG_ADDR
enable bit is set. If the enable bit is not set, a PCI I/O transaction is generated.
Table 17-5. PCI CFG_DATA Field Descriptions
Table 17-6. PCI INT_ACK Field Descriptions
Figure 17-4. PCI CFG_DATA Register
Figure 17-5. PCI INT_ACK Register
Figure
for usage of PCI CFG_ADDR.
for usage of CFG_DATA.
17-3.
All zeros
All zeros
Description
Data
Data
Description
Figure
17-5.
and
and
Section 17.4.2.11.3, “Agent
Section 17.4.2.11.3, “Agent
Access: Read/Write
Access: Read Only
PCI Bus Interface
17-15
31
31