MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 114

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Overview
A block diagram of the integrated security engine’s internal architecture is shown in
interface module is designed to transfer 64-bit words between the internal bus and any register inside the
SEC.
An operation begins with a write of a pointer to a crypto-channel fetch register that points to a data packet
descriptor. The channel requests the descriptor and decodes the operation to be performed. The channel
then requests the controller to assign crypto-execution units and fetch the keys, IVs, and data needed to
perform the given operation. The controller satisfies the requests by assigning execution units to the
channel and by making requests to the master interface. As data is processed, it is written to the individual
execution unit’s output buffer and then back to system memory via the bus interface module.
The SEC functionality is compatible with code written for the integrated security engine present in the
Freescale MPC8541E and MPC8555E devices.
1.3.9
The MPC8533E provides two inter-IC (IIC or I
serial bus that provides a simple, efficient method of data exchange between devices. The synchronous,
multi-master bus of the I
microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. The two-wire bus
(serial data SDA and serial clock SCL) minimizes the interconnections between devices. I
connection of additional devices to the bus for expansion and system development.
The I
data corruption if two or more masters attempt to control the bus simultaneously. This feature allows for
complex applications with multiprocessor control. The I
unit, a clocking unit, and a control unit. The dual I
filtering rejects spikes on the bus.
1-16
2
C controller is a true multimaster bus which includes collision detection and arbitration that prevents
Interface
Master/
Slave
I
2
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
C Controllers
Crypto-
channel
Crypto-
channel
Crypto-
channel
Crypto-
channel
Figure 1-2. Integrated Security Engine Functional Blocks
2
C allows the MPC8533E to exchange data with other I
Control
PKEU
2
C) interfaces. The I
2
C units support general broadcast mode, and on-chip
FIFO
FIFO
DEU
2
C controller consists of a transmitter/receiver
MDEU
FIFO
FIFO
2
AESU
FIFO
FIFO
C bus is a two-wire, bidirectional
AFEU
FIFO
FIFO
2
C devices such as
FIFO
FIFO
KEU
Freescale Semiconductor
Figure
2
FIFO
RNG
C allows the
1-2. The bus