MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 609

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

13.3.1.9
The ULSRs are read-only registers that monitor the status of the data transfer on the UART buses. To
isolate the status bits from the proper character received through the UART bus, software should read the
ULSR and then the URBR.
Figure 13-11
Table 13-16
Freescale Semiconductor
Bits Name
0
1
2
3
4
TEMT Transmitter empty.
THRE Transmitter holding register empty.
RFE Receiver FIFO error.
Offset 0x505
FE
Reset
BI
W
R
0 This bit is cleared when there are no errors in the receiver FIFO or on a read of the ULSR with no remaining
1 Set to one when one of the characters in the receiver FIFO encounters an error (framing, parity, or break
0 Either or both the UTHR or the internal transmitter shift register has a data character. In FIFO mode, a data
1 Both the UTHR and the internal transmitter shift register are empty. In FIFO mode, both the transmitter FIFO
0 The UTHR is not empty.
1 A data character has transferred from the UTHR into the internal transmitter shift register. In FIFO mode, the
Break interrupt.
0 This bit is cleared when the ULSR is read or when a valid data transfer is detected (that is, STOP bit is received).
1 Received data of logic 0 for more than START bit + Data bits + Parity bit + one STOP bits length of time. A new
Framing error.
0 This bit is cleared when ULSR is read or when a new character is loaded into the URBR from the receiver shift
1 Invalid STOP bit for receive data (only the first STOP bit is checked). In FIFO mode, this bit is set when the
0x605
describes the fields of the ULSRs.
shows the bits in the ULSRs.
receiver FIFO errors.
interrupt)
character is in the transmitter FIFO or the internal transmitter shift register.
and the internal transmitter shift register are empty.
transmitter FIFO contains no data character.
character is not loaded until SIN returns to the mark state (logic 1) and a valid START is detected. In FIFO mode,
a zero character is encountered in the FIFO (the zero character is at the top of the FIFO). In FIFO mode, only
one zero character is stored.
register.
character that detected a framing error is encountered in the FIFO (that is the character at the top of the FIFO).
An attempt to resynchronize occurs after a framing error. The UART assumes that the framing error (due to a
logic 0 being read when a logic 1 (STOP) was expected) was due to a STOP bit overlapping with the next
START bit, so it assumes this logic 0 sample is a true START bit and then will receive the following new data.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Line Status Registers (ULSR0, ULSR1)
RFE
0
0
TEMT
1
1
Figure 13-11. Line Status Register (ULSR)
Table 13-16. ULSR Field Descriptions
THRE
1
2
BI
0
3
Description
FE
0
4
PE
0
5
OE
0
6
Access: Read only
DR
0
7
DUART
13-15