MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 434

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Programmable Interrupt Controller
10.3.6.4
The shared message signaled interrupt vector/priority registers have the same field and format as the
GTVPRs. These registers are read/write.
Table 10-38
10.3.6.5
The shared message signaled interrupt destination registers contain the destination bits for the shared
message signaled interrupt. A shared message signaled interrupt can be directed to one of the processors
by setting the appropriate bit in the shared message signaled interrupt destination register. Only one of the
bits corresponding to destination processors may be set. The behavior is more than one bit is set is not
defined. This register also contains the external pin and critical interrupt fields that can be programmed to
direct the interrupt to the external pin or critical interrupt pin of the processor, respectively.
These registers are read/write, as shown in
10-38
12–15 PRIORITY Priority. Sets interrupt priority. The highest priority is 15; the lowest is 0 (interrupt generation disabled).
16–31 VECTOR Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register is examined
Offset 0x5_1C00, 0x5_1C20, 0x5_1C40, 0x5_1C60, 0x5_1C80, 0x5_1CA0, 0x5_1CC0, 0x5_1CE0
2–11
Reset
Offset 0x5_1C10, 0x5_1C30, 0x5_1C50, 0x5_1C70, 0x5_1C90, 0x5_1CB0, 0x5_1CD0, 0x5_1CF0
Bits
Reset 0
0
1
W
W
R
R
MSK
0
1
0
Name
MSK
—
Figure 10-34. Shared Message Signaled Interrupt Vector/Priority Register (MSIVPR n )
A
0
1
Figure 10-35. Shared Message Signaled Interrupt Destination Registers (MSIDR n )
A
0
describes the bits of the MSIVPRn.
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
0
Shared Message Signaled Interrupt Vector/Priority Register (MSIVPR n )
Shared Message Signaled Interrupt Destination Register (MSIDR n )
0
0
Mask. Mask interrupts from this source.
0 If the mask bit is cleared while the corresponding IPR bit is set, an interrupt request is generated.
1 Further interrupts from this source are disabled.
This bit is always set to a 1 following reset.
Activity (read only). Indicates whether an interrupt has been requested or that it is in-service.
0 No current interrupt activity associated with this source.
1 The interrupt bit for this source in the IPR or ISR is set.
The PRIORITY value should not be changed while the A bit is set.
Reserved.
and the interrupt associated with this vector has been requested.
0
0
0
0
0
0
0
—
0
0
Table 10-38. MSIVPR n Field Descriptions
0
0
0
0
0
0
0
11 12
0
Figure
0
0
PRIORITY
0
0
10-35.
0
0
—
0
15 16
0
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VECTOR
0
0
0 0 0 0 0 0 0
0
Freescale Semiconductor
0 0 0 0 0 0 0
Access: Mixed
Access: Mixed
30
P0
31
1
31