MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1307
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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T
U
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Tenure. The period of bus mastership. There can be separate address bus tenures and data
Throughput. The measure of the number of instructions that are processed per clock
Time-division multiplex (TDM). A single serial channel used by several channels taking
Transaction. A complete exchange between two bus devices. A transaction is typically
Transfer termination. Signal that refers to both signals that acknowledge the transfer of
Translation lookaside buffer (TLB). A cache that holds recently-used
User mode. The operating state of a processor used typically by application software. In
bus tenures.
cycle.
turns.
comprised of an address tenure and one or more data tenures, which may overlap
or occur separately from the address tenure. A transaction may be minimally
comprised of an address tenure only.
individual beats (of both single-beat transfer and individual beats of a burst
transfer) and to signals that mark the end of the tenure.
user mode, software can access only certain control registers and can access only
user memory space. No privileged operations can be performed. Also referred to
as problem state.
page table
Glossary-9
entries.
Glossary
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