MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 593

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.7
The SEC may be disabled by setting DEVDISR[SEC]. (See
(DEVDISR),”
should not be enabled/disabled during normal operation.
Freescale Semiconductor
48–55 CHN3_BUS_PR_CNT Channel 3 bus priority counter.This counter is used by the controller to determine when
56–63 CHN4_BUS_PR_CNT Channel 4 bus priority counter. This counter is used by the controller to determine when
Bits
Power-Saving Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Name
for more information on this register.). The clocks to the SEC are active by default. The SEC
Table 12-62. Master Control Register (MCR) Field Descriptions (continued)
Channel 3 has been denied access to the bus long enough to warrant immediate elevation to
top priority.
Note: If set to zero, the CHN4_BUS_PR_CTR must also be set to zero, and the controller will
Channel 4 has been denied access to a needed on-chip resource long enough to warrant
immediate elevation to top priority.
Note: If set to zero, the CHN3_BUS_PR_CTR must also be set to zero, and the controller will
assign access to the bus on a pure round robin basis. If set to non-zero,
CHN4_BUS_PR_CTR must also be set to a different, non-zero value.
assign access to the bus on a pure round robin basis. If set to non-zero,
CHN3_BUS_PR_CTR must also be set to a different, non-zero value.
Section 19.4.1.12, “Device Disable Register
Description
Security Engine (SEC) 2.1
12-115