MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1171
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 19-9
19.4.1.7
GPPORCR stores the value sampled from the local bus address/data signals, LAD[0:31], during POR, as
described in
inform the operating system about initial system configuration. Typical interpretations include circuit
board type, board ID number, or a list of available peripherals.
GPPORCR is shown in
Table 19-10
19.4.1.8
Shown in
general-purpose I/O. Note that when these signals are enabled as general-purpose I/O signals, they are read
and written through GPINDR and GPOUTDR described in
Data Register (GPINDR),”
Section 19.5.2, “General-Purpose I/O Signals,”
Freescale Semiconductor
0–31 POR_CFG_VEC General-purpose POR configuration vector sampled from local bus address/data signals at the
Bits
Offset 0xE_0020
Reset n
27–31
0–25
Bits
26
W
R
0
Figure
SEC_CFG
Name
n
describes the bit settings of PORDEVSR2.
Name
describes the bit settings of GPPORCR.
Section 4.4.3.20, “General-Purpose POR Configuration.”
General-Purpose POR Configuration Register (GPPORCR)
General-Purpose I/O Control Register (GPIOCR)
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
n
n
19-8, GPIOCR contains the enable bits for each group of pins that may be used for
n n
negation of HRESET. Note that if nothing is driven on these signals during reset, the value of this
register is indeterminate.
Reserved
0 Enables the SEC in 2:1 (CCB CLK: SEC CLK) mode with respect to e500 core complex bus
1 Enables the SEC in 3:1 (CCB CLK: SEC CLK) mode with respect to e500 core complex bus
Reserved
SEC frequency ratio configuration (See
(CCB) clock
(CCB) clock
Figure
n
Figure 19-7. POR Configuration Register (GPPORCR)
and
n n
Table 19-9. PORDEVSR2 Field Descriptions
19-7.
Section 19.4.1.9, “General-Purpose Output Data Register (GPOUTDR).”
Table 19-10. GPPORCR Field Descriptions
n
n n
n
n n
describes the use of general-purpose I/O signals.
POR_CFG_VEC
n
Section 4.4.3.3, “SEC Frequency Ratio
n n
Description
Description
Section 19.4.1.10, “General-Purpose Input
n
n n
Software can use this value to
n
n n
n
n n
Configuration.)
Access: Read Only
n
n n
Global Utilities
n
19-11
31
n
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