MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 487

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The channel can signal to the host that it is done with a descriptor via interrupt or by a writeback of the
descriptor header into host memory. In the case of writeback, the value written back is identical to the
header that was read, with the exception that a DONE field is set to all 1s. In addition, the channel can be
configured to write back other status fields that indicate the result of ICV checking (if any). The user can
opt to enable this signaling at end of every descriptor, or at the end of selected descriptors. For more
information about configuring signaling, see
1–4 (CCCRn).”
Many security protocols involve both encryption and hashing of packet payloads. To accomplish this
without requiring two passes through the data, channels can configure data flows through more than one
EU. In such cases, one EU is designated the primary EU, and the other as the secondary EU. The primary
EU receives its data from memory via the controller, and the secondary EU receives its data by snooping
the SEC buses.
There are two types of snooping.
In the SEC, the secondary EU is always the MDEU.
For more information, refer to
12.1.4
The controller manages on-chip resources, including the individual execution units (EUs), FIFOs, the
master/slave interface to the MPC8533E internal system bus, and the other internal buses that connect the
remaining modules. The controller receives service requests from the master/slave interface and from the
crypto-channels, and schedules the required activities. The controller provides for two ways of operating
the execution units:
The system bus interface and access to system memory are critical factors in performance, and the 64-bit
master/slave interface of the SEC controller allows it to achieve performance unattainable on secondary
buses.
Freescale Semiconductor
7. Upon completion, unload results from output FIFOs and context registers and write them to
8. If multiple services are requested, go back to step 3.
9. Release the EUs.
10. If done notification is enabled, perform this notification.
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•
•
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external memory using pointers in the descriptor buffer.
Input data can be fed to the primary EU and the same input data snooped by the secondary EU.
This is called in-snooping.
Output data from the primary EU can be snooped by the secondary EU. This is called out-snooping.
Channel-controlled access—A channel can request a particular service from any available
execution unit. This is the normal operating condition.
Host-controlled access—The host can move data into and out of any execution unit directly
through memory-mapped EU registers. This is typically only used for debug.
Controller
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 12.5, “Crypto-Channels.”
Section 12.5.1.1, “Crypto-Channel Configuration Registers
Security Engine (SEC) 2.1
12-9