MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 532

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
All descriptors other than the final descriptor must output the intermediate message digest for the next
descriptor to reload as MDEU context.
SSL-MAC operations cannot be spread across a sequence of descriptors.
Additional information on descriptors can be found in
12.4.4.3
Shown in
HMAC generation. MDEU supports at most 64 bytes of key. MDEU generates a key size error if the value
written to this register exceeds 64 bytes.
12.4.4.4
The MDEU data size register, shown in
The data size field is a 21-bit signed number. Values written to this register are added to the current register
value. Multiple writes are allowed. The MDEU processes data when there is a positive value in this register
and there is data available in the MDEU input FIFO. (Negative values can arise in inbound processing,
when it is necessary to hold back data from the MDEU until the pad length has been decrypted.)
Since the MDEU does not support bit offsets, bits 61–63 must be written as 0, and are always read as zero.
Furthermore, when the CONT bit of the MDEU mode register is high, the data size must be a multiple of
the 512-bit block size (i.e. bits 55–63 must be written as 0). Violating either of these conditions causes a
data size error (DSE in the MDEU interrupt status register).
This register is cleared when the MDEU is reset or re-initialized. At the end of processing, its contents
have been decremented down to zero (unless there is an error interrupt).
12-54
Offset MDEU 0x3_6008
Reset
W
R
0
Figure
Table 12-29. Mode Register —HMAC Generated Across a Sequence of Descriptors
MDEU Key Size Register (MDEUKSR)
MDEU Data Size Register (MDEUDSR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
12-31, this value indicates the number of bytes of key memory that should be used in
Bits
56
59
60
CONT
HMAC
Field
INIT
Figure 12-31. MDEU Key Size Register
Figure
Descriptor
1 (on)
1 (on)
1 (on)
12-32, indicates the number of bits of data to be processed.
First
—
All zeros
Section 12.3, “Descriptor Overview.”
Descriptor(s)
Middle
Value
1 (on)
0 (off)
0 (off)
Descriptor
0 (off)
0 (off)
1 (on)
Final
Freescale Semiconductor
Access: Read/Write
56 57
KEY SIZE
63