MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 951
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 16-8
Table 16-8
16.3.1.4
The source attributes registers, shown in
DMA operation. Stride mode is enabled by setting SATRn[SSME].
If SATRn[SBPATMU] is cleared, the target interface is derived from the local access ATMU mapping and
the transaction is obtained from the value specified in SATRn[SREADTTYPE] using the local address
space category.
Freescale Semiconductor
29–31
0–26
Offset 0x10C
Reset
Bits
27
28
W
R
28–31
0–27
Bit
0x18C
0x20C
0x28C
0
CLNDA Current link descriptor address. Contains the current descriptor address of the buffer descriptor in memory.
EOSIE End-of-segment interrupt enable
Name
—
—
describes the fields of the CLNDARn.
shows CLNDARn.
ECLNDA Current link descriptor extended address (upper 4 bits of 36-bit address)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Source Attributes Registers (SATR n )
Name
The descriptor must be aligned to a 32-byte boundary. (This is the lower portion of the 36-bit address formed
by CLNDAR n [CLNDA] and ECLNDAR n [ECLNDA].)
Reserved
0 Do not generate an interrupt upon completion of the current DMA transfer for the current link descriptor.
1 Generate an interrupt upon completion of the current DMA transfer for the current link descriptor.
Reserved
—
Figure 16-8. Current Link Descriptor Address Registers (CLNDAR n )
Reserved
Table 16-7. ECLNDAR n Field Descriptions
Table 16-8. CLNDAR n Field Descriptions
Figure
CLNDA
16-9, contain the transaction attributes to be used for the
All zeros
Description
Description
26
—
27
Access: Read/Write
EOSIE
28
DMA Controller
29
—
16-15
31
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