MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 665
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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14.4.3
The LBC provides an SDRAM interface (machine) for the local bus. The machine provides the control
functions and signals for Intel PC133 and JEDEC-compliant SDRAM devices. Each bank can control an
SDRAM device on the local bus.
14.4.3.1
The memory controller supports any SDRAM configuration with the restrictions that all SDRAM devices
that reside on the bus should have the same port size and timing parameters (as defined in LSDMR).
Figure 14-34
lines. Note that address signals A[2:0] of the SDRAM connect directly to LA[27:29], address signal A10
connects to the LBCs dedicated LSDA10 signal, while the remaining address bits (except A10) are latched
from LAD[20:26].
Freescale Semiconductor
Register
BR0
SDRAM Machine
shows an example connection between the LBC and a 32-bit SDRAM device with 12 address
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Supported SDRAM Configurations
DECC
MSEL
ATOM
Field
XBA
WP
BA
PS
V
Table 14-25. Boot Bank Field Values After Reset
0000_0000_0000_0000_0
From signal during reset.
Setting
000
00
00
00
0
1
Register
OR0
BCTLD
CSNT
XACS
EHTR
SETA
TRLX
Field
XAM
ACS
SCY
EAD
AM
0000_0000_0000_0000_0
Setting
1111
00
11
0
1
1
0
1
1
1
Local Bus Controller
14-47
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