MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 639

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.3.1.7
The local bus SDRAM mode register (LSDMR), shown in
pertaining to SDRAM.
Table 14-12
Freescale Semiconductor
11–13
Offset 0x094
Reset
8–10
Bits
2–4
5–7
0
1
W
R
— RFEN
0
BSMA
Name
RFEN
1
OP
—
—
—
describes LSDMR fields.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SDRAM Machine Mode Register (LSDMR)
2
OP
Reserved
Refresh enable. Indicates that the SDRAM requires refresh services.
0 Refresh services are not required.
1 Refresh services are required.
SDRAM operation. Selects the operation that occurs when the SDRAM device is accessed.
Reserved
Bank select multiplexed address line. Selects which address signals serve as the 2-bit bank-select
address for SDRAM. Note that only 4-bank SDRAMs are supported.
000 LA12:LA13
001 LA13:LA14
010 LA14:LA15
011 LA15:LA16
Reserved
4 5
—
Figure 14-10. SDRAM Machine Mode Register (LSDMR)
7
Value
8
000
001
010
011
100
101
110
111
BSMA
Table 14-13. LSDMR Field Descriptions
10 11
Normal operation
Auto refresh
Self refresh
Mode Register write
Precharge bank
Precharge all banks
Activate bank
Read/write without valid data transfer
—
13 14
RFCR
100 LA16:LA17
101 LA17:LA18
110 LA18:LA19
111 LA19:LA20
Meaning
16 17
All zeros
PRETOACT ACTTORW BL
Description
Figure
19
20
14-10, is used to configure operations
Normal operation
Initialization
Power-down mode or debug
Initialization
Debug
Initialization
Debug
Debug
22
23 24 25 26 27 28
—
Use
WRC — BUFCMD
Access: Read/Write
Local Bus Controller
29
30 31
14-21
CL