MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 482

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
Upon completion of a descriptor, the channel checks the next entry in its fetch FIFO, and, if non-zero, the
channel requests a burst read of the next descriptor.
For most packets, the entire payload is too long to fit in an execution unit’s input or output FIFO. The SEC
then uses a flow control scheme for reading and writing data. The channel directs the controller to read
bursts of input as necessary to keep refilling the input FIFO, until the entire payload has been fetched.
Similarly, the channel directs the controller to write bursts of output whenever enough accumulates in the
execution unit’s output FIFO.
12.1.1
As a crypto-acceleration block, the SEC controller has been designed for easy use and integration with
existing systems and software. All cryptographic functions are accessible through descriptors. A descriptor
specifies a cryptographic function to be performed, and contains pointers to all necessary input data and
to the places where output data is to be written. Some descriptor types perform multiple functions to
facilitate particular protocols. A sample descriptor is shown in
Each descriptor contains eight long-words (64 bits each), consisting of the following:
12-4
Field Name
•
Pointer0
Pointer1
Pointer2
Pointer3
Pointer4
Pointer5
Pointer6
Length0
Length1
Length2
Length3
Length4
Length5
Length6
Extent0
Extent1
Extent2
Extent3
Extent4
Extent5
Extent6
Header
One long-word of header—The header describes the required services and encodes information
that indicates which EUs to use and which modes to set. It also indicates whether notification
should be sent to the host when the descriptor operation is complete.
Descriptors
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0x2053_1E08_0000_0000
(32 or 36-bit pointer)
(32 or 36-bit pointer)
(32 or 36-bit pointer)
(32 or 36-bit pointer)
(32 or 36-bit pointer)
(32 or 36-bit pointer)
(32 or 36-bit pointer)
Value
1500
1500
16
16
12
0
0
8
0
8
0
0
8
0
Table 12-1. Example Descriptor
Example header for IPsec ESP outbound using DES and MD-5
Number of bytes in authenticate key
Unused
Pointer to authentication key
Number of bytes in authentication-only data
Unused
Pointer to authentication-only data
Length of input context (IV)
Unused
Pointer to input context
Number of bytes in cipher key
Unused
Pointer to cipher key
Number of bytes of data to be ciphered
Unused
Pointer to input data to perform ciphering upon
Number of bytes of data after ciphering
Number of bytes in authentication result (ICV)
Pointer to location where cipher output is to be written, followed by ICV
Length of output Context (IV)
Unused
Pointer to location where altered Context is to be written
Table
Description
12-1.
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