MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 743

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

All accesses to and from the registers must be made as 32-bit accesses. There is no support for accesses of
sizes other than 32 bits. Writes to reserved register bits must always store 0, as writing 1 to reserved bits
may have unintended side-effects. Reads from unmapped register addresses return zero. Unless otherwise
specified, the read value of reserved bits in mapped registers is not defined, and must not be assumed to
be 0.
This section of the document defines the memory map and describes the registers in detail. The buffer
descriptor is described in
The ten-bit interface (TBI) module MII registers are also described in this section. The TBI registers are
defined like PHY registers and, as such, are accessed via the MII management interface in the same way
the PHYs are accessed. For detailed descriptions of the TBI registers (the MII register set for the ten-bit
interface) refer to
15.5.1
Each of the two eTSECs is allocated 4 Kbytes of memory-mapped space. The space for each eTSEC is
divided as indicated in
15.5.2
Table 15-4
offsets to the memory map table are defined for both eTSECs. That is, eTSEC1 starts at 0x2_4000 address
offset and eTSEC3 starts at 0x2_6000 address offset. The registers for eTSEC1 are listed in
but the registers for the other eTSEC are not. Note that the registers are the same for eTSEC3 except that
the offset changes as previously explained and as noted at the end of
In this table and in the register figures and field descriptions, the following access definitions apply:
Freescale Semiconductor
•
•
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
lists the address, name, and a cross-reference to the complete description of each register. The
Top-Level Module Memory Map
Detailed Memory Map
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 15.5.4, “Ten-Bit Interface (TBI).”
Table
Section 15.6.7, “Buffer Descriptors.”
Address Offset
C00–C3F
A00–AFF
B00–BFF
15-3.
000–0FF
100–2FF
300–4FF
500–5FF
600–7FF
800–8FF
900–9FF
C–FFF
Table 15-3. Module Memory Map Summary
eTSEC general control/status registers
eTSEC transmit control/status registers
eTSEC receive control/status registers
MAC registers
RMON MIB registers
Hash table registers
—
FIFO control/status registers
DMA system registers
Lossless Flow Control registers
—
Function
Table
Enhanced Three-Speed Ethernet Controllers
15-4.
Table
15-4,
15-13