MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 647
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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14.3.1.14
The transfer error address register (LTEAR) is shown in
Table 14-20
14.3.1.15
The local bus configuration register (LBCR) is shown in
Table 14-21
Freescale Semiconductor
Offset 0x0D0
Reset
0–31
Bits
Bits
Bits
1–7
30
31
0
W
R
LDIS
0
Offset 0x0C0
Reset
Name
Name
Name
LDIS
—
—
A
V
W
1
R
describes LTEAR fields.
describes LBCR fields.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Transaction address for the error. Holds the 32 lsbs of the 34-bit address of the transaction resulting in an
error.
Local bus disable
0 Local bus is enabled
1 Local bus is disabled. No internal transactions will be acknowledged.
Reserved
Reserved
Error attribute capture is valid. Indicates that the captured error information is valid
0 Captured error attributes and address are not valid
1 Captured error attributes and address are valid
Transfer Error Address Register (LTEAR)
Local Bus Configuration Register (LBCR)
—
Figure 14-17. Transfer Error Address Register (LTEAR)
7
Table 14-19. LTEATR Field Descriptions (continued)
BCTLC AHD
Figure 14-18. Local Bus Configuration Register
8
9
Table 14-20. LTEAR Field Descriptions
Table 14-21. LBCR Field Descriptions
10
11
—
13
LPBSE EPAR
14
All zeros
All zeros
Description
Description
Description
A
Figure
Figure
15
16
14-17.
14-18.
BMT
23
24
Access: Read/Write
Local Bus Controller
Access: Read/Write
—
31
14-29
31
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