MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1246

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Debug Features and Watchpoint Facility
Table 21-22
21.3.3
This section describes the context ID registers. The current context ID register (CCIDR) and programmed
context ID registers (PCIDR) are set by software and facilitate debugging complex software.
21.3.3.1
The programmed context ID register (PCIDR), shown in
context ID. This register can be configured to trigger watchpoint events when its value matches the current
context ID register (CCIDR), as controlled by WMCR0[ECEN] and WMCR0[NECEN]. See
Section 21.3.1.1, “Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1),”
information.
Table 21-23
21-22
0–31
0–31
Bits
Bits
Offset 0x068
Offset 0x0A0
Reset
Reset
W
W
R
R
Name
Name
TBAD Trace buffer access data. Corresponds to the lower 32 bits of the data read from the trace buffer or to be
PCID
0
0
Context ID Registers
describes the TBADR field.
describes the PCIDR field.
Programmed Context ID Register (PCIDR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Programmed context ID. Contains the user-programmed context ID. Compared with current context ID for
context-sensitive event triggering
written into the trace buffer, depending on whether software is accessing the array with a read or a write.
Figure 21-16. Trace Buffer Access Data Register (TBADR)
Figure 21-17. Programmed Context ID Register (PCIDR)
Table 21-22. TBADR Field Descriptions
Table 21-23. PCIDR Field Descriptions
All zeros
All zeros
TBAD
PCID
Description
Description
Figure
21-17, contains the user-programmed
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
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31
31

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