MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 845

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.5.4.2
The eTSEC’s TBI Implements the receive portion of the physical coding sublayer as found in Clause 36
of IEEE 802.3z. The Receive portion includes the Synchronization state machine. In SerDes mode, the
eTSEC first attempts to acquire synchronization on the link by examining received symbols. Once
synchronization is acquired, received packets are decoded and sent across the Receive GMII interface. In
GMII mode, the GMII signals are passed through to the MAC.
15.5.4.2.1
The eTSEC examines received symbols looking for the seven bit ‘comma’ string embedded in some
special symbols. Both the idle ordered_set and the Configuration ordered_set contain a symbol which has
the comma. Once a certain number of codes with comma are detected, the eTSEC is considered to have
acquired synchronization.
15.5.4.2.2
Once synchronization is acquired, ordered_sets are decoded. If Configuration ordered_sets are received, the
eTSEC decodes the two octet data field and the sixteen-bit Configuration data is stored and used to
Auto-Negotiate with the link partner. in the Receive Configuration Register (RXCR[15:0]) an internal
register used to receive all the link partners informations and used to compare to local ability during
negotiation. Not visible to user. If, during Auto-Negotiation an invalid symbol is detected, Auto-Negotiation
re-starts. After Auto-Negotiation is completed the TBI MII Status Register SR[AN done] in set. In this mode,
packets may be received from the link partner.
15.5.4.3
This section describes the TBI MII registers. All of the TBI registers are 16 bits wide. The TBI registers are
accessed at the offset of the TBI physical address. The eTSEC’s TBI physical address is stored in the TBIPA
register. Writing to the TBI registers is performed in a way similar to writing to an external PHY, by using
the MII management interface. By using TBIPA in place of the PHY address, in the MIIMADD[PHY
Address] field, and setting the MIIMADD[Register Address] to the appropriate address offset that
corresponds to the register that one wants to read or write (see
MIIMCOM[read cycle]) or write (writing to MIIMCON[PHY control]) to the TBI block. Refer to the TBI
physical address register in
MII register set in
registers and are only used for test and control of the eTSEC TBI block. The TBI’s TBI control register (TBI)
is for configuring the eTSEC ten-bit interface block. However, because this TBI block has an MII
management interface (just like any other PHY), it has an IEEE 802.3 register called the control register
(CR).
Freescale Semiconductor
Address
Offset
0x00
TBI Receive Process
TBI MII Set Register Descriptions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Synchronization
Auto-Negotiation for 1000BASE-X
Table
Control (CR)
15-110. Notice that jitter diagnostics and TBI control are not IEEE 802.3 required
TEN-BIT INTERFACE (TBI) REGISTERS
Section 15.5.3.1, “eTSEC General Control and Status
Table 15-110. TBI MII Register Set
Name
Access
Table
R/W
1
15-110), the user can read (set
Enhanced Three-Speed Ethernet Controllers
16 bits
Size
Registers,” and the TBI
15.5.4.3.1/15-116
Section/page
15.5.4/15-114
15-115