MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 968

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DMA Controller
16.4.1.4.2
On a channel continue, the descriptor at the current list descriptor (CLSDARn and ECLSDARn) address
register is refetched to get the next list descriptor address field as updated by software. The channel halts
if NLSDARn[EOLSD] is still set. If not, the next list descriptor address is copied into the CLSDARn and
ECLSDARn registers and the channel continues with another descriptor fetch of the current list descriptor
address. As a result, two list descriptor fetches always exist after channel continue before the first link
descriptor fetch and the first transfer.
16.4.1.5
Software can abort a previously initiated transfer by setting MRn[CA]. Once the DMA channel controller
detects a zero-to-one transition of MRn[CA], it finishes the current sub-block transfer and halts all further
activity. The controller then waits for all previously initiated transfers from the specified channel to drain
and clears SRn[CB]. Successful completion of a software initiated abort request can be recognized by
MRn[CA] being set and SRn[CB] being cleared. Obviously, if the controller was already halted because
of an error condition (SRn[TE] is set), or the channel has completed all transfers, then SRn[CB] being
cleared may not signify that the controller entered a halt state due to the abort request.
16.4.1.6
MRn[BWC] specifies how much data to allow a specific channel to transfer before allowing the next
channel to use the shared data transfer hardware. This promotes equitable bandwidth allocation between
channels. However, if only one channel is busy, hardware overrides the specified bandwidth control size
value. The DMA controller allows a channel to transfer up to 1 Kbyte at a time when no other channel is
active.
16.4.1.7
Table 16-21
busy (SRn[CB]), transfer error (SRn[TE]), and channel continue (MRn[CC]) bits.
16-32
MR n [CS] SR n [CB] SR n [TE] MR n [CC]
—
0
0
0
0
0
0
1
1
defines the state of a channel based on the values of the channel start (MRn[CS]), channel
0
0
0
0
1
1
1
0
0
Extended Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Channel Abort
Bandwidth Control
Channel State
0
0
1
1
0
0
1
0
0
—
0
1
0
1
0
1
0
1
Idle state. This is the state of the bits out of reset.
Channel continue unexpected. Channel remains idle
Error occurred after software halted the channel.
Channel Continue unexpected. Channel remains in error halt state
Software halted channel. The channel was busy and software cleared MR n [CS].
Channel remains in halt state.
The channel has encountered an error condition and it is trying to halt.
Ready to start a transfer, or transfer completed
Continue transfer (only meaningful in chaining mode, not direct mode). In direct
mode, the channel continue has no effect.
Table 16-21. Channel State Table
Channel State
Freescale Semiconductor