MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 805
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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Table 15-47
15.5.3.5.10 MII Management Status Register (MIIMSTAT)
The MIIMSTAT register is read only by the user.
register.
Table 15-48
15.5.3.5.11 MII Management Indicator Register (MIIMIND)
The MIIMIND register is read-only by the user.
register.
Freescale Semiconductor
16–31
16–31
0–15
0–15
Bits
Bits
O
Offset eTSEC1:0x2_4530
Reset
Offset eTSEC1:0x2_4534
Reset
W
R
W
R
PHY Control If written, an MII Mgmt write cycle is performed using this 16-bit data, the pre-configured PHY address
PHY Status Following an MII Mgmt read cycle, the 16-bit data can be read from this location. Its default value is
0
Name
0
Name
—
describes the fields of the MIIMCON register.
describes the fields of the MIIMSTAT register.
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
0x0000.
Reserved
(at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register Address]). Its default
value is 0x0000.
Figure 15-46. MII Mgmt Indicator Register Definition
Figure 15-45. MIIMSTAT Register Definition
—
Table 15-48. MIIMSTAT Field Descriptions
Table 15-47. MIIMCON Field Descriptions
—
Figure 15-46
Figure 15-45
All zeros
All zeros
15 16
Description
Description
describes the definition for the MIIMIND
describes the definition for the MIIMSTAT
Enhanced Three-Speed Ethernet Controllers
28
PHY Status
Not Valid
29
Access: Read only
Access: Read only
Scan
30
Busy
15-75
31
31
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