MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 515

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.2.6
The DEU interrupt status register, shown in
register can only be set if the corresponding bit of the DEU interrupt control register is zero (see
Section 12.4.2.7, “DEU Interrupt Control Register
If the DEU interrupt status register is non-zero, the DEU halts and the DEU error interrupt signal is
asserted to the controller (see
is being operated through channel-controlled access, then an interrupt signal is generated to the channel to
which this EU is assigned. The EU error then appears in bit 55 of the channel pointer status register (see
Table
Table 12-19
Freescale Semiconductor
Address DEU 0x3_2030
0–49
Bits Name
Bits
50
Reset
62
63
W
R
12-55) and generates a channel error interrupt to the controller.
KPE
Name
0
—
RD
ID
describes DEU interrupt status register fields.
Reserved
Key parity error. Defined parity bits in the keys written to the key registers did not reflect odd parity correctly. (Note
that key register 2 and key register 3 are checked for parity only if the appropriate DEU mode register bit indicates
triple DES. Also, key register 3 is checked only if key size reg = 24. Key register 2 is checked only if key size reg
= 16 or 24.)
0 No error detected
1 Key parity error
DEU Interrupt Status Register (DEUISR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 DEU is not signaling done
1 DEU is signaling done
Reset done. This status bit, when high, indicates that DEU has completed its reset sequence, as reflected in
the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating
the EU is ready for operation.
Table 12-18. DEU Status Register Field Descriptions (continued)
Table 12-19. DEU Interrupt Status Register Field Descriptions
—
Section 12.6.5.3, “Interrupt Status Register
Figure 12-18. DEU Interrupt Status Register
(Section 12.6.5.3, “Interrupt Status Register
49
Figure
KPE IE ERE CE KSE DSE ME AE OFE IFE IFU IFO OFU OFO
50
51
(DEUICR)”).
12-18, records occurrences of errors. Each bit in this
All zeros
Description
52
Description
53
54
55
(ISR)”).
56
(ISR)”). In addition, if the DEU
57
58
59
Security Engine (SEC) 2.1
60
Access: Read-only
61
62
12-37
63