MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 579

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.5.1.4
Each channel contains a fetch address FIFO to store a queue of pointers to descriptors for the channel to
process.
The fetch address FIFOs, shown in
be processed. In typical operation, the host CPU creates a descriptor in memory containing all relevant
mode and location information for the SEC, then launches the SEC by writing the address of the descriptor
to the fetch FIFO.
The fetch FIFO can hold up to 24 descriptor pointers at a time. When the end of the current descriptor is
reached, the descriptor pointed to by the next location in the fetch FIFO is read to launch the next
descriptor.
The fetch address is written into the FIFO only if the write includes the least-significant byte (bits 56–63).
If extend address enable is high (see the EAE bit in
written before the fetch address or concurrent with it. Specifying a FETCH_ADRS of 0 causes the channel
to generate an error and stop.
Writing a descriptor pointer to the fetch FIFO while the FIFO is full will result in a single overflow
interrupt to advise the user that the descriptor pointer was not successfully written to the fetch FIFO. The
channel will continue processing and software can check the fetch FIFO counter in the crypto-channel
pointer status register before attempting to re-enqueue the descriptor pointer. If a second descriptor pointer
is written to the fetch FIFO before the single the single overflow error is cleared, the channel generates a
double overflow error interrupt and stop processing descriptors. The channel can be restarted by setting
the continue bit in the crypto-channel configuration register, or completely reset by writing the reset bit in
the same register.
Table 12-58
Freescale Semiconductor
Address Channel_1 0x3_01148
28–31
32–63 FETCH_ADRS Fetch address. Pointer to system memory location of a descriptor the host wants the SEC to fetch.
0–27
Bits
Reset
W
R
Channel_2 0x3_01248
Channel_3 0x3_01348
Channel_4 0x3_01448
0
Name
EPTR
describes the fetch FIFO fields.
—
Fetch FIFO Address Registers 1–4 (FF n )
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved — Set to zero.
Extended pointer. Concatenated as the top 4 bits of the FETCH_ADRS when EAE is high (see the
EAE bit in Table 1-51 on page 1-116).
—
Table 12-58. Fetch FIFO Field Descriptions
Figure
Figure 12-76. Fetch FIFO
12-76, contain the addresses of the first byte of descriptors to
27 28
Table
EPTR
All zeros
31 32
12-50), then the extended fetch address must be
Description
FETCH_ADRS
Security Engine (SEC) 2.1
Access: Write-only
12-101
63